Техническая Спецификация для Intel Xeon 3040 HH80557KH0362M
Модели
HH80557KH0362M
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
91
Features
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the IA-32 Intel
Normal Mode or the HALT Power Down state. See the IA-32 Intel
®
Architecture
Software Developer's Manual Volume 3: System Programmer's Guide for more
information.
information.
The system can generate a STPCLK# while the processor is in the HALT powerdown
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT powerdown state, the processor will process bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown
state
must be enabled via the BIOS for the processor to remain within
its specification.
The processor automatically transitions to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor first switches to the lower bus ratio and then transitions to
the lower VID.
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor first switches to the lower bus ratio and then transitions to
the lower VID.
While in Extended HALT state, the processor processes bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will
processor exits the Extended HALT state, it will
resume operation at the lower
frequency,
first transition the VID to the original value and then change the bus ratio
back to the original value.
6.2.3
Stop Grant
and Extended Stop Grant
State
s
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer
to the BIOS Writer’s Guide for Extended Stop Grant configuration information. Refer to
the following sections for details about the Stop Grant and Extended Stop Grant states.
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer
to the BIOS Writer’s Guide for Extended Stop Grant configuration information. Refer to
the following sections for details about the Stop Grant and Extended Stop Grant states.
6.2.3.1
Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to V
(allowing the level to return to V
TT
) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.