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17
NI 5441 Specifications
Onboard Clock
(Internal VCXO)
Phase-Locked Loop (PLL) Reference Clock
Specification
Value
Comments
Clock Source
Internal sample clocks can either be locked to a Reference 
Clock using a phase-locked loop or be derived from the 
onboard VCXO frequency reference.
Frequency 
Accuracy
±25 ppm
Specification
Value
Comments
Sources
1. PXI_CLK10 (backplane connector)
2. CLK IN (SMB front panel connector)
The PLL 
Reference Clock 
provides the 
reference 
frequency for the 
PLL.
Frequency 
Accuracy
When using the PLL, the Frequency Accuracy of the 
NI 5441 is solely dependent on the Frequency Accuracy 
of the PLL Reference Clock Source.
Lock Time
Typical: 70 ms.
Maximum: 200 ms.
Frequency 
Range
5 MHz to 20 MHz in increments of 1 MHz.
Default of 10 MHz.
The PLL Reference Clock Frequency has to be accurate 
to
±50 ppm.
Duty Cycle 
Range
40% to 60%
Exported PLL 
Reference 
Clock 
Destinations
1. PFI<0..1> (SMB front panel connectors)
2. PXI_Trig<0..7> (backplane connector)