Справочник Пользователя для Emerson PMPPC7448

 Exception Handling

PmPPC7448 User’s Manual

Disable Precharge for ARTRY*, SHD0*, and SHD1* pins
0 Signals driven high when negated
1 Signals not driven high when negated

Dynamic Frequency Switching divide-by-four mode
0 Disabled
1 Enabled

Dynamic Frequency Switching divide-by-two mode
0 Disabled
1 Enabled

PLL Configuration bit 5 (PLL CFG[5]), read only

PLL Configuration bit 0 (PLL CFG[0]), read only

PLL Configuration bit 1 (PLL CFG[1]), read only

PLL Configuration bit 2 (PLL CFG[2]), read only

PLL Configuration bit 3 (PLL CFG[3]), read only

PLL Configuration bit 4 (PLL CFG[4]), read only

Address Broadcast Enable for sync, eieio
0 Disabled
1 Enabled

Address Broadcast Enable for dcbf, dcbst, dcbi, icbi, tlbie, tlbsync
0 Disable address broadcasting for cache and TLB control operations
1 Enable address broadcasting for cache and TLB control operations 

Each CPU exception type transfers control to a different address in the vector table. The 
vector table normally occupies the first 0x2000 bytes of RAM (with a base address of 
0000,0000

16

) or ROM (with a base address of F800,0000

16

). An unassigned vector position 

may be used to point to an error routine or for code or data storage. 

 lists the pro-

cessor exceptions starting with the highest priority per the following four exception classes.

Nonmaskable exceptions have priority over all other exceptions. These exceptions cannot 
be delayed and do not wait for completion of any precise exception handling.

Negated

0

1

Bus/2

Negated

1

0

Core

Negated

1

1

Core/2