Справочник Пользователя для Cypress CY7C68033

Document #: 001-04247 Rev. *D

Page 4 of 33

The NX2LP-Flex features an 8- or 16-bit ‘FIFO’ bidirectional
data bus, multiplexed on I/O ports B and D. 

The default firmware image implements an 8-bit data bus in
GPIF Master mode. It is recommended that additional inter-
faces added to the default firmware image use this 8-bit data
bus.

During the start-up sequence, internal logic checks for the
presence of NAND Flash with valid firmware. If valid firmware
is found, the NX2LP-Flex loads it and operates according to
the firmware. If no NAND Flash is detected, or if no valid
firmware is found, the NX2LP-Flex uses the default values
from internal ROM space for manufacturing mode operation.
The two modes of operation are described in the section

”Normal Operation Mode” on page 5 and  ”Manufacturing

0

SCON1

PSW

ACC

B

1

SP

SBUF1

2

DPL0

3

DPH0

4

5

6

7

PCON

8

TCON

SCON0

IE

IP

T2CON

9

TMOD

SBUF0

A

TL0

RCAP2L

B

TL1

RCAP2H

C

TH0

TL2

D

TH1

TH2

E

F