Справочник Пользователя для Cypress CY7C2561KV18
PRELIMINARY
CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
CY7C2563KV18, CY7C2565KV18
Document Number: 001-15887 Rev. *E
Page 10 of 29
Application Example
shows two QDR-II+ used in an application.
Figure 1. Application Example
Table 3. Truth Table
The truth table for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follows.
The truth table for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follows.
Operation
K
RPS WPS
DQ
DQ
DQ
DQ
Write Cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
L-H
H
L
D(A) at K(t + 1)
↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑
Read Cycle:
(2.5 cycle Latency)
Load address on the rising
edge of K; wait two and
half cycles; read data on
two consecutive K and K
rising edges.
L-H
L
X
Q(A) at K(t + 2)
↑ Q(A + 1) at K(t + 3)↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 4)↑
NOP: No Operation
L-H
H
H
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Previous State
Previous State
BUS MASTER
(CPU or ASIC)
DATA IN
DATA OUT
Address
Source K
Source K
Source K
Vt
Vt
Vt
R
R
D
A
A
K
SRAM #2
RQ = 250 ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
D
A
A
K
SRAM #1
RQ = 250 ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
RPS
WPS
BWS
BWS
CLKIN1/CLKIN1
R = 50ohms, Vt = V /2
DDQ
R
ODT
ODT
ODT
R
CLKIN2/CLKIN2
Notes
4. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
5. Device powers up deselected with the outputs in a tri-state condition.
6. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
7. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
9. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
10. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
11. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
6. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
7. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
9. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
10. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
11. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.