Справочник Пользователя для Intel S5000PSL

To boot the system, the system BIOS on the server board uses a dedicated I

2

C bus to retrieve DIMM information needed to program 

the MCH memory registers. The following table provides the I

2

C addresses for each DIMM socket. 

 

DIMM A1 

0xA0 

DIMM A2 

0xA2 

DIMM B1 

0xA0 

DIMM B2 

0xA2 

DIMM C1 

0xA0 

DIMM C2 

0xA2 

DIMM D1 

0xA0 

DIMM D2 

0xA2 

 

The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features. These 
features include the Intel

®

 x4 Single Device Data Correction (Intel

®

 x4 SDDC) for the following: 

ƒ

 

Memory error detection and correction 

ƒ

 

Memory scrubbing 

ƒ

 

Retry on correctable errors 

ƒ

 

Memory built-in self-test 

ƒ

 

DIMM sparing 

ƒ

 

Memory mirroring 
 

See the Intel

 for more information about these features.