Справочник Пользователя для Intel S3420GP
IntelP®P Server Board S3420GP TPS
Functional Architecture
3.2.5.1
TableMemory Subsystem Operating Frequency Determinat
The rules for determining the operating frequency of the memory channels are simple, but not
necessarily straightforward. There are several limitin
necessarily straightforward. There are several limitin
ion
g factors, including the number of DIMMs
R), or
ponent – the slowest DIMM or the IMC – determines the
IMMs are installed on a channel, the speed is limited to 1066 MHZ.
d to 800 MHz.
ry channels that belong to
processor sockets.
er channel), which can support a maximum of six
tel
®
Server Board S3420GP is
rated Memory Controller (IMC).
channels and groups DIMMs on the board into an
memory.
entifiers on the silkscreen on the board provide information about the
essor socket to which they belong. For example, DIMM_A1 is
ot on channel A.
Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the
follo in
follo in
Existing DDR3 DIMM population
timization techniques used by the Intel
®
Nehalem processor to maximize memory
In the Independent Channel mode, all DDR3 channels operate independently. Slot-to-slot DIMM
matching is not required across channels (for example, A1 and B1 do not have to match each
other in terms of size, organization, and timing). DIMMs within a channel do not have to match
in terms of size and organization, but they operate in the minimal common frequency. Also,
Independent Channel mode can be used to support single DIMM configuration in channel A and
in the Single Channel mode.
matching is not required across channels (for example, A1 and B1 do not have to match each
other in terms of size, organization, and timing). DIMMs within a channel do not have to match
in terms of size and organization, but they operate in the minimal common frequency. Also,
Independent Channel mode can be used to support single DIMM configuration in channel A and
in the Single Channel mode.
on a channel and organization of the DIMM - that is, either single-rank (SR), dual-rank (D
quad-rank (QR):
quad-rank (QR):
The speed of the processor’s IMC is the maximum speed possible.
The speed of the slowest com
maximum frequency, subject to further limitations.
maximum frequency, subject to further limitations.
A single 1333-MHz DIMM (SR or DR) on a channel may run at full 1333-MHz speed.
If two SR/DR D
A single QR RDIMM on a channel is limited to 1066 MHz.
Two QR RDIMMs or a mix of QR + SR/DR on a channel is limite
3.2.5.2
Memory Subsystem Nomenclature
1. DIMMs are organized into physical slots on DDR3 memo
2. The memory channels are identified as channels A, B.
3. For Intel
3. For Intel
®
Xeon
®
3400 Series, each socket can support a maximum of six DIMM
sockets (three DIMM sockets p
DIMM sockets.
DIMM sockets.
®
®
4. The Intel Xeon 3400 Series processor on the In
populated on the processor socket. It has an Integ
The IMC provides two DDR3
autonomous
The IMC provides two DDR3
autonomous
5. The DIMM id
channel and the proc
the first sl
the first sl
3.2.5.3
Memory Upgrade Rules
w g factors:
DDR3 DIMM characteristics
Op
bandwidth
bandwidth
Revision 1.0
Intel order number E65697-003
19