Справочник Пользователя для Intel US15W

 

User’s Manual 

 19 

    Document Number: 320264 

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Two PS/2 ports.  

Note:  The two PS/2 ports are for a legacy keyboard and mouse. The keyboard plugs into the 

bottom port and the mouse plugs into the top port. 

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EMA support 

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Wake/runtime SCI events 

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Power sequencing control 

A TSOP socket houses the flash device (ST Microelectronics P/N# M50FW080) that 
stores the system EFI firmware. The EFI firmware can be programmed through a 

Microsoft MS-DOS* or Windows*-based utility.

 

Crown Beach implements a header at J9B4 to support TPM 1.2 specification compliant 
devices. The same header can be used for legacy connections, allowing other SIO 

solutions to provide floppy, COM, Parallel, and PS/2 functionality. 

Crown Beach provides three ports with the following features: 

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All ports are SD rev1.1 specification compliant and MMC rev4.0 specification 
compliant. 

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All ports operate to 48 MHz. Ports 0 and 1 support 4-bit operation. Port 2 supports 

8-bit operation. 

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Slot 2 is also routed (with stuffing options) to the PCI Express* Mini Card for 
wireless solutions. 

The Crown Beach CRB uses a CK-540 clock solution. The BSEL [2:1] signals driven by 
the processor are used by the CK-540 to configure the FSB frequency. 

An on-board battery maintains power to the real time clock (RTC) when in a 
mechanical off state (G3 state).