Справочник Пользователя для Intel GME965

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316704-001 / Development Kit User’s Manual 

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SDVO interface via PCI Express* x16 connector provides maximum display 

flexibility 

o

 

Can drive up to two display outputs 

The development board supports DDR2 533/667 main memory. Two 200-pin SODIMM 

connectors (one per channel) on the development board support unbuffered, non-ECC, 

single and double-sided DDR2 533/667 MHz SODIMMs. These SODIMMs provide the 

ability to use up to 1 Gbit technology for a maximum of 4 GBytes system memory. 

Note:  Memory that utilizes 128 MBit technology is not supported on the Mobile Intel

®

 

GME965 Express Chipset. 

Note:  The SODIMM connectors are on the back side of the development board. 

Caution:  Standby voltage may be applied to the SODIMM sockets when the system is in the 

 

S3, S4 and S5 states. Therefore, do not insert or remove SODIMMs unless the 

 

system is unplugged. 

The Mobile Intel

®

 GME965 Express Chipset GMCH’s Direct Media Interface (DMI) 

provides high-speed bi-directional chip-to-chip interconnect for communication with 

the ICH8-M. 

The development board has five options for displaying video: VGA, LVDS, TV-Out, 

SDVO, or PCI Express* Graphics. SDVO and PCI Express* Graphics are multiplexed on 

the same pins within the Mobile Intel

®

 GME965 Express Chipset. The development 

board contains one SDVO/PCI Express* Graphics Slot (J6B2) for a PCI Express* 

compatible graphics card or an SDVO compatible graphics card, one LVDS connector 

(J6F1), one TV-Out connector (J2A1), and one 15-pin VGA connector (J2A2). 

A standard 15 pin D-Sub connector on the rear panel provides access to the analog 

output of the Mobile Intel

®

 GME965 Express Chipset. This can be connected to any 

capable analog CRT or flat panel display with compatible input. 

When used in conjunction with the other display options, the displays can operate in 

Dual Independent mode. This allows unique content to appear on each display at 

unique refresh rates and timings. 

The development board provides one 50-pin LVDS video interface connector. The 

interface is compliant with the SPWG 3.5 (for 18-bpp panels) and proposed SPWG 4.0 

(for 24-bpp panels) standards.