Справочник Пользователя для Intel 41110
Intel® 41110 Serial to Parallel PCI Bridge Design Guide
25
General Routing Guidelines
6.4
Power Distribution and Decoupling
Have ample decoupling to ground, for the power planes, to minimize the effects of the switching
currents. Three types of decoupling are: the bulk, the high-frequency ceramic, and the inter-plane
capacitors.
currents. Three types of decoupling are: the bulk, the high-frequency ceramic, and the inter-plane
capacitors.
•
Bulk capacitance consist of electrolytic or tantalum capacitors. These capacitors supply large
reservoirs of charge, but they are useful only at lower frequencies due to lead inductance
effects. The bulk capacitors can be located anywhere on the board.
reservoirs of charge, but they are useful only at lower frequencies due to lead inductance
effects. The bulk capacitors can be located anywhere on the board.
•
For fast switching currents, high-frequency low-inductance capacitors are most effective.
Place these capacitors as close to the device being decoupled as possible. This minimizes the
parasitic resistance and inductance associated with board traces and vias.
Place these capacitors as close to the device being decoupled as possible. This minimizes the
parasitic resistance and inductance associated with board traces and vias.
•
Use an inter-plane capacitor between power and ground planes to reduce the effective plane
impedance at high frequencies. The general guideline for placing capacitors is to place high-
frequency ceramic capacitors as close as possible to the module.
impedance at high frequencies. The general guideline for placing capacitors is to place high-
frequency ceramic capacitors as close as possible to the module.
6.4.1
Decoupling
Inadequate high-frequency decoupling results in intermittent and unreliable behavior.
A general guideline recommends that you use the largest easily available capacitor in the lowest
inductance package. For specific decoupling requirements for a 41110 application please refer to
inductance package. For specific decoupling requirements for a 41110 application please refer to
.
6.5
Trace Impedance
All signal layers require controlled impedance 60
Ω +/- 15%, microstrip or stripline for add-in card
applications. Selecting the appropriate board stack-up to minimize impedance variations is very
important. When calculating flight times, it is important to consider the minimum and maximum
trace impedance based on the switching neighboring traces. Use wider spaces between traces, since
this can minimize trace-to-trace coupling, and reduce cross talk.
important. When calculating flight times, it is important to consider the minimum and maximum
trace impedance based on the switching neighboring traces. Use wider spaces between traces, since
this can minimize trace-to-trace coupling, and reduce cross talk.
When a different stack up is used the trace widths must be adjusted appropriately. When wider
traces are used, the trace spacing must be adjusted accordingly (linearly).
traces are used, the trace spacing must be adjusted accordingly (linearly).
It is highly recommended that a 2D Field Solver be used to design the high-speed traces. The
following Impedance Calculator URL provide approximations for the trace impedance of various
topologies. They may be used to generate the starting point for a full 2D Field solver.
following Impedance Calculator URL provide approximations for the trace impedance of various
topologies. They may be used to generate the starting point for a full 2D Field solver.
The following website link provides a useful basic guideline for calculating trace parameters: