Справочник Пользователя для Fujitsu FR81S
CHAPTER 25: 16-BIT OUTPUT COMPARE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 16-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
Case #1 where the free-run timer is in up/down count mode
⋅
The timing of data transfer from the compare buffer of the output compare is when there is a compare
clear match of the free-run timer.
⋅
When there is an output compare output match, the output is in inverted mode.
Notes:
⋅
When the compare register value is set to "0000
H
", the output compare output is set to "1" regardless of
the count value of the free-run timer (or reset to "0" when CMOD: bit12 = 1 in OCS).
⋅
When the compare register value is set to "FFFF
H
", the output compare output is reset to "0" regardless
of the count value of the free-run timer (or set to "1" when CMOD: bit12 = 1 in OCS).
⋅
No comparison is made when there is a match between the compare clear register value of the free-run
timer and the compare register value of the output compare. Note that a compare match occurs only
once at the time of starting the free-run timer when the initial value of the free-run timer is same as the
compare clear register value. If, at this time, both the compare clear register value and the compare
register value are set to "FFFF
H
", the output compare output is reset to "0" regardless of the count value
of the free-run timer.
Figure 5-13 Case #1 Where the Free-run Timer Is in Up/Down Count Mode
CFFF
H
BFFF
H
0000
H
Count value
Time
Compare buffer
register
BFFF
H
Compare register
Compare output
initial value 0
CFFF
H
BFFF
H
BFFF
H
0000
H
FFFF
H
0000
H
CFFF
H
BFFF
H
0000
H
FFFF
H
Compare output
initial value 1
BFFF
H
For CMOD=0
MB91520 Series
MN705-00010-1v0-E
984