Справочник Пользователя для Fujitsu FR81S
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CHAPTER 27: UP/DOWN COUNTER
5. Interrupt
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
Notes:
· Once an interrupt request is generated, the up/down counter stops operation until the interrupt request
flag is cleared.
· The CMPF bit in the counter control register (CCR) changes to "1" if the value matches in counting up, if
the value of the reload compare register (RCR) is reloaded, or if the value has already matched when the
up/down counter is started.
up/down counter is started.
· For the clearing of the counter and the reload timing, see "
■ Clear Events" and "■ Reload Event" in "6.
Operation and Setting Procedure Examples".
· Once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt
request will be issued when the interrupt is enabled.
· To enable the generation of an interrupt request, perform one of the following operations:
· Clear the current interrupt request before enabling the generation of an interrupt request.
· Clear the current interrupt request when enabling the interrupt.
· Clear the current interrupt request when enabling the interrupt.
· For interrupt vector numbers used for issuing an interrupt request, see "APPENDIX C. List of Interrupt
Vector".
· Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control
registers (ICR00 to ICR47). For information on interrupt level setting, see the chapter of "Interrupt
Control(Interrupt Controller)".
Control(Interrupt Controller)".
MB91520 Series
MN705-00010-1v0-E
1027