Справочник Пользователя для Fujitsu FR81S
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
When this bit is set to "0":
⋅
Serial clock output mark level is set to "H".
⋅
Transmission data is output in synchronization with a falling edge of the serial clock in the normal
transfer while it is output in synchronization with a rising edge of the serial clock in the SPI transfer.
⋅
Reception data is sampled at a rising edge of the serial clock in the normal transfer while it is sampled at
a falling edge of the serial clock in the SPI transfer.
When this bit is set to "1":
⋅
Serial clock output mark level is set to "L".
⋅
Transmission data is output in synchronization with a rising edge of the serial clock in the normal
transfer while it is output in synchronization with a falling edge of the serial clock in the SPI transfer.
⋅
Reception data is sampled at a falling edge of the serial clock in the normal transfer while it is sampled at
a rising edge of the serial clock in the SPI transfer.
Notes:
⋅
Set this bit when transmission and reception are disabled (SCR:TXE=RXE=0).
⋅
Set this bit when serial clock output is disabled (SCKE=0).
⋅
After SCINV is set, set reception enable (SCR: RXE=1).
⋅
Set this bit when transmission and reception are disabled (TXE=RXE=0).
⋅
This bit is used in one of cases below.
⋅
When chip select pin is disabled (SCSCR:CSEN3-0=“0000”b)
⋅
While in slave mode (SCR:MS=0)
⋅
When data format of chip select is disabled (ESCR:CSFE=0)
⋅
When data format of chip select is enabled (ESCR:CSFE=1) and serial chip select pin 0 is active
[I
2
C]
⋅
This bit enables or disables the output of reception interrupt request to the CPU.
⋅
When the RIE bit and the reception data flag bit (SSR:RDRF) are set to "1", or any of the error flag bits
(ORE) is set to "1", a reception interrupt request will be output.
Note:
Set this bit to "0" when receiving data with the use of INT bit of I
2
C bus control register (IBCR) while
DMA mode is disabled (SSR:DMA=0).
[bit2] BDS/TIE (Bit Direction Select/Transmit Interrupt Enable): Transfer direction selection bit/
transmission interrupt enable bit
[LIN-UART]
LIN-UART does not use this bit. Writing a value to this bit does not affect the operation.
[UART][CSIO]
⋅
This bit selects whether to transfer the transfer serial data from the least significant bit (LSB-first,
BDS=0) or from the most significant bit (MSB-first, BDS=1).
Notes:
⋅
Set this bit when transmission and reception are disabled (SCR:TXE=RXE=0).
⋅
[CSIO] This bit is used in one of cases below.
⋅
When chip select pin is disabled (SCSCR:CSEN3-0=“0000”b)
⋅
While in slave mode (SCR:MS=0)
⋅
When data format of chip select is disabled (ESCR:CSFE=0)
⋅
When data format of chip select is enabled (ESCR:CSFE=1) and serial chip select pin 0 is active
MB91520 Series
MN705-00010-1v0-E
1333