Справочник Пользователя для Fujitsu FR81S
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
19
4.6. Main Timer Control Register : MTMCR (Main clock
TiMer Control Register)
The bit configuration of the main timer control register is shown.
This register controls the main timer which runs with the main clock (MCLK).
MTMCR : Address 0512
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MTIF
MTIE
MTC
MTE
MTS[3:0]
Initial value
0
0
0
0
1
1
1
1
Attribute
R(RM1),W
R/W
R(RM0),W
R/W
R1,WX
R/W
R/W
R/W
Because the main timer is used for generating the oscillation stabilization wait time for main clock (MCLK),
it can be used only after the main clock oscillation is stabilized.
The main timer is cleared when the main clock oscillation stops (MCEN=0) or it is in the stop mode.
When the operation of the main timer is not allowed (MTE=0), the main timer stops except that it is waiting
for a main clock oscillation stabilization. The write operation to this register becomes enabled only when
MCRDY=1 except for MTIE. Thus a main timer clear executed by MTC=1 in main clock oscillation
stabilization wait status (MCEN=1 and MCRDY=0) is not effective.
When the main timer stops (MTE=0) it will be cleared and while being cleared MTC=1 will be read out.
At that time the main timer interrupt flag is not set. The main timer overflow period (MTS[3:0]) should be
changed at the time when the main timer stops (MTE=0).
When rewriting MTE=1 with 0, the main timer will continue to operate until the MTC bit is set to "0". In this
interval, the main timer interrupt flag may turn to "1". When writing MTC=1, the main timer will continue to
operate until the MTC bit is set to "0". In this interval, the main timer interrupt flag may turn to "1". If a
MTE=0 to 1 rewrite and a MTC=1 write occur at the same time, the operation starts after a clear takes place,
so the start will be delayed.
[bit7] MTIF (Main clock Timer Interrupt Flag) : Main timer interrupt flag
The flag to indicate that an overflow happens in the interval for which the main timer has selected.
When the MTIE bit is "1" and this bit is set, a main timer interrupt request is generated.
Clear factor
⋅
"0" write
⋅
A DMA transfer is generated by the main timer interrupt.
Set factor
⋅
An overflow occurred in the interval set by MTS[3:0]
⋅
The end of oscillation stabilization wait time of the main clock after setting MCEN=0 to
1.
⋅
The end of oscillation stabilization wait time of the main clock (MCLK) after exiting
the stop mode. (A set will not take place at the end of oscillation stabilization wait time
after reset by SINIT.)
Writing "1" to this bit is ineffective.
When the MTIE bit is set to "0", this bit will not be cleared by DMA transfer.
For read-modify-write instructions, "1" will be read out.
If a set factor and a clear factor occur at the same time, the set factor will take precedence.
MB91520 Series
MN705-00010-1v0-E
180