Справочник Пользователя для Fujitsu FR81S
APPENDIX
B. List of Interrupt Vector
FUJITSU SEMICONDUCTOR LIMITED
APPENDIX
FUJITSU SEMICONDUCTOR CONFIDENTIAL
81
Interrupt factor
Interrupt
number
Interrupt
level
Offset
Default
address for
TBR
RN
*
Decimal
Hexa-
decimal
Base timer 1 IRQ0
61
3D
ICR45
308
H
000FFF08
H
45(*5)
Base timer 1 IRQ1
-
-
-
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304
H
000FFF04
H
-
Delayed interrupt
63
3F
ICR47
300
H
000FFF00
H
-
System reserved
(Used for REALOS.)
64
40
-
2FC
H
000FFEFC
H
-
System reserved
(Used for REALOS.)
65
41
-
2F8
H
000FFEF8
H
-
Used with the INT instruction.
66
|
255
42
|
FF
-
2F4
H
|
000
H
000FFEF4
H
|
000FFC00
H
-
* It does not support the DMA transfer request by the interrupt generated from a peripheral to which no RN
(Resource Number) is assigned.
(*1) The status of the multi-function serial interface does not support the DMA transfer by the I
2
C reception.
(*2) The reload timer ch.4 to ch.7 does not support the DMA transfer by the interrupt.
(*3) The PPG ch.24 to ch.47 does not support the DMA transfer by the interrupt.
(*4) The clock calibration unit does not support the DMA transfer by the interrupt.
(*5) It does not support the DMA transfer by the interrupt because of the RAM ECC bit error.
(*6) The 32-bit free-run timer ch.3 to ch.5 does not support the DMA transfer by the interrupt.
(*8) It does not support the DMA transfer by the external low-voltage detection interrupt.
MB91520 Series
MN705-00010-1v0-E
2291