Справочник Пользователя для Fujitsu FR81S
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CHAPTER 7: RESET
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
32
5.3.3. Reset Issue Delay Counter
The reset issue delay counter is shown.
As soon as a reset request is generated, the 8-bit reset issue delay counter starts counting. If the delay cycle
specified by the bit7 to bit5: RDLY[2:0] bits of the RSTCR register has elapsed without a reset being issued
and the counter overflows (= reset timeout occurs), an irregular reset will be issued.
The RDLY[2:0] bit of the RSTCR will be initialized by a reset. This bit can be rewritten for once only after a
reset is released. If the delay cycle is set for a short time, it is more likely to generate an irregular reset. If the
delay cycle is set for a long time, it might take a long time for a reset to be issued since the generation of a
reset factor.
MB91520 Series
MN705-00010-1v0-E
285