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CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
4.22. DMA Request Clear Register 23 : ICSEL23 (Interrupt
Clear SELect register 23)
The bit configuration of DMA request clear register 23 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #45).
ICSEL23: Address 0417
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
MFS_SEL0[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] MFS_SEL0[1:0] (MFS_Selection) : Interrupt clear selection bits for MFS ch.8 (reception
completion) / ICU0 / ICU1
MFS_SEL0[1:0]
Clear target
00
Multi-function serial ch.8 reception completion
01
16-bit ICU0
10
16-bit ICU1
11
Reserved (Does not clear any)
Note:
Setting MFS_SEL0[1:0]= "11" is prohibited. During this setting, no interrupt clear will be selected.
MB91520 Series
MN705-00010-1v0-E
376