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CHAPTER 12: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: INTERRUPT CONTROL (INTERRUPT CONTROLLER)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
5
3. Configuration
This section explains the configuration of the interrupt control (interrupt controller).
Figure 3-1 Block Diagram
ICR47
ICR00
ICR01
5
5
5
5
5
5
48
P
e
r
iphe
r
al inter
r
upt
v
ector
n
umber
Inter
r
upt l
e
v
el
W
a
k
eup
gene
r
ation circuit
B
us
a
cc
es
s
Inter
r
upt l
e
v
el
and inter
r
upt
v
ector
dete
r
mination and
Inter
r
upt
*
* : NMI or (XBS RAM double bit error generation) or (Backup RAM double bit error generation)
or TPU violation or Error generation at internal bus diagnosis.
MB91520 Series
MN705-00010-1v0-E
466