Справочник Пользователя для Fujitsu FR81S
CHAPTER 17: PPG
6. Notes
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
68
27. In the PPG communication mode, the register that becomes valid or invalid as follows.
Valid registers:
Software trigger (STRG)
Count clock selection (CKS1, CKS0)
PPG output mask selection (PGMS)
Trigger input selection (EGS1, EGS0)
Interrupt request enable (IREN)
Interrupt factor selection (IRS1, IRS0)
PPG output enable (OE)
PPG output polarity selection (OSEL)
PPG timer (PTMR), GATE function control (GATEC)
PPG communication mode data reading selection (CMDSEL)
PPG communication mode enable (CMD)
Timing Point Capture interrupt (IRS2)
PPG communication data register Empty flag (REMP)
PPG communication data shift register Empty flag (SREMP)
High format cycle setting (PHCSR)
Low format cycle setting (PLCSR)
High format duty setting (PHDUT)
Low format duty setting (PLDUT)
Communication mode data setting (PCMDDT)
Communication mode data bit length setting (PCMDWD)
Invalid registers:
Timer operation enable (CNTE)
Mode selection (MDSE)
Restart enable (RTRG)
PPG output waveform selection (OWFS)
Interrupt request flag (IRQF)
PPG cycle setting (PCSR)
PPG duty setting (PDUT)
Timing Point Capture enable (TPC)
Start Delay enable (STRD)
Start Delay value setting (PSDR)
Timing Point Capture value setting (PTPC)
28. During the PPG communication operation, do not change any of the following: the count clock selection
(CKS1, CKS0), the trigger input edge selection (EGS1, EGS0), the PPG output polarity selection (OSEL),
the PPG communication mode data reading selection (CMDSEL), and the communication mode data bit
length setting (PCMDWD)
If any of the above bits is changed during the PPG communication operation, disable PPG communication
operation before reconfiguring the register.
MB91520 Series
MN705-00010-1v0-E
609