Справочник Пользователя для Fujitsu FR81S
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
48
Figure 5-4 Block Diagram (32-bit Reload Timer Operation)
BT0PCSR
32-bit mode
T32=1
CKS
PCL K
EG S
2
3
2
0
2
7
2
8
STR G
CTE N
CTE N
MDS E
16
BT0TMR
T32
OSE L
UDIE
TG IE
ch.0
ch.1
BT1TMR )
BT1PCSR
T32=0
16
IRQ0
IRQ1
Edge
detection
BT1PCSR : Base timer 1 cycle setting register (BT1PCSR)
BT1TMR : Base timer 1 timer register (BT1TMR)
BT0PCSR : Base timer 0 cycle setting register (BT0PCSR)
BT0TMR : Base timer 0 timer register (BT0TMR)
Load
Count clock
Down counter
Underflow
enabled
Count
Count clock
Load
Down counter
Underflow
Count
Output waveform
(TOUT signal)
Invert control
Toggle
Division
Edge
detection
Peripheral clock
External clock
(ECK signal)
External activation
Interrupt
Trigger
Trigger
Timer enabled
Underflow
Count
circuit
trigger (TGIN signal)
enabled
enabled
generation
source
generation
interrupt request
interrupt request
MB91520 Series
MN705-00010-1v0-E
681