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CHAPTER 20: RELOAD TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
5.1.5. Counter Operation Selection
The counter operation selection is shown below.
Select the operation in case of counter underflow in the mode selection bits (bit15, bit14:MOD[1:0] of the
TMCSR register) and the reload operation enabling bit (bit4:RELD of the TMCSR register). For details of
operation in each mode, see the section of each counter operation.
TMCSR register) and the reload operation enabling bit (bit4:RELD of the TMCSR register). For details of
operation in each mode, see the section of each counter operation.
Table 5-3 List of Counter Operation
MOD[1:0] RELD
Operation in case of underflow
Counter operation
name
00
0
Stop the counter with 0xFFFF
Single one-shot
1
Reload TMRLRA
Single reload
01
0
(1) Reload TMRLRB
(2) Stop the counter with 0xFFFF
(See “5.3.3 Dual One-shot Operation”)
Dual one-shot
1
Reload TMRLRA and TMRLRB in turns
Dual reload
10
0
Stop the counter with 0xFFFF
Compare one-shot
1
Reload TMRLRA
Compare reload
11
0
Stop the counter with 0xFFFF
Capture one-shot
1
Reload TMRLRA
Capture reload
MB91520 Series
MN705-00010-1v0-E
748