Справочник Пользователя для Fujitsu FR81S
CHAPTER 20: RELOAD TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
39
5.3.4. Dual Reload Operation
The dual one-shot operation is shown below.
When bit15, bit14:MOD[1:0] of the TMCSR register =01, and bit4:RELD of the TMCSR register =1, the
timer performs the dual reload operation.
timer performs the dual reload operation.
In dual reload operation, the values of TMRLRA and TMRLRB are loaded alternatively and decrement the
counters for each load, that is, loads TMRLRA onto the counter and decrements the counter, and if an
underflow occurs, loads TMRLRB onto the counter and decrement the counter, and if an another underflow
occurs, loads TMRLRA onto the counter and decrements the counter, and so on.
counters for each load, that is, loads TMRLRA onto the counter and decrements the counter, and if an
underflow occurs, loads TMRLRB onto the counter and decrement the counter, and if an another underflow
occurs, loads TMRLRA onto the counter and decrements the counter, and so on.
When bit5:OUTL=0 of the TMCSR register, the value of TMRLRA represents the time interval between a
timer activation (TOUT output is in L level) to a toggling of the TOUT output to "H", and the value of
TMRLRB represents the time interval of H width of the TOUT output.
timer activation (TOUT output is in L level) to a toggling of the TOUT output to "H", and the value of
TMRLRB represents the time interval of H width of the TOUT output.
If an underflow (UF-A) occurs at the down count after loading a value from the TMRLRA, the following
operation will be performed.
operation will be performed.
⋅ Sets bit2:UF bit of the TMCSR register.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Loads TMRLRB to the counter.
⋅ Inverts TOUT output.
⋅ Starts a down count from TMRLRB.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Loads TMRLRB to the counter.
⋅ Inverts TOUT output.
⋅ Starts a down count from TMRLRB.
If an underflow (UF-B) occurs at the down count after loading a value from the TMRLRB, the following
operation will be performed.
operation will be performed.
⋅ Sets bit2:UF bit of the TMCSR register.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Loads TMRLRA to the counter.
⋅ Inverts TOUT output.
⋅ Starts a down count from TMRLRA.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Loads TMRLRA to the counter.
⋅ Inverts TOUT output.
⋅ Starts a down count from TMRLRA.
MB91520 Series
MN705-00010-1v0-E
766