Справочник Пользователя для AMD LX 900@1.5W

AMD Geode™ LX Processors Data Book

119

CPU Core Register Descriptions

33234H

5.5.2.12 IF Test Data MSR (IF_TEST_DATA_MSR)

12:8

BLOCK

Block Identifier.

00h: Target RAM 0 (Way 0). (Default)
01h: Target RAM 1 (Way 0).
02h: Target RAM 2 (Way 0).
03h: Target RAM 3 (Way 0).
04h: Target RAM 4 (Way 1).
05h: Target RAM 5 (Way 1).
06h: Target RAM 6 (Way 1).
07h: Target RAM 7 (Way 1).
08h: Target RAM 8 (Way 2).
09h: Target RAM 9 (Way 2).
0Ah: Target RAM 10 (Way 2).
0Bh: Target RAM 11 (Way 2).
0Ch: Target RAM 12 (Way 3).
0Dh: Target RAM 13 (Way 3).
0Eh: Target RAM 14 (Way 3).
0Fh: Target RAM 15 (Way 3).
10h: Tag RAM 0 (Way 0).
11h: Tag RAM 1 (Way 1).
12h: Tag RAM 2 (Way 2).
13h: Tag RAM 3 (Way 3).
14h: L0 COF cache.
15h: Return stack.

7:0

INDEX

Block Index. (Default = 00h)

When accessing a Tag RAM or a Target RAM, the index is the address of the RAM loca-
tion (0-255).

When accessing the L0 COF cache, indexes 0-1 refer to the 2 tag entries, 4-5 refer to the
2 source addresses, 8-9 refer to the 2 target addresses, and 12-13 refer to the 2 return
addresses.

When accessing the return stack, indexes 0-7 refer to the 8 non-speculative return
addresses, indexes 8-15 refer to the IF speculative return addresses, and address 16
refers to the valid bits, indexes 17-24 refer to the ID speculative return addresses.

MSR Address

00001109h

Type

R/W

Reset Value

00000000_xxxxxxxxh

IF_TEST_ADDR_MSR Bit Descriptions (Continued)

Bit

Name Description

IF_TEST_DATA_MSR Register Map for Target RAMs

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

TGT

IF_TEST_DATA_MSR Bit Descriptions for Target RAMs

Bit

Name Description

63:32

RSVD

Reserved.

31:0

TGT

COF Target.