Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
173
CPU Core Register Descriptions
33234H
5.5.2.76 Data Cache Data MSR (DC_DATA_MSR)
5.5.2.77 Data Cache Tag MSR (DC_TAG_MSR)
MSR Address
00001891h
Type
R/W
Reset Value
00000000_00000000h
DC_DATA_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DC_DATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DC_DATA
DC_DATA_MSR Bit Descriptions
Bit
Name
Description
63:0
DC_DATA
Data Cache Data. QWORD data to read from or write to the cache line buffer. The buffer
is filled from the cache data array on a read to DC_TAG_MSR (MSR 00001892h) or
DC_TAG_I_MSR (MSR 00001893h), and the buffer is written to the cache data array on
a write to DC_TAG_MSR or DC_TAG_I_MSR MSRs. The DC_DSEL field in the
DC_INDEX_MSR (MSR 00001890h[17:16]) selects which QWORD in the buffer is
accessed by DC_DATA, and each access to DC_DATA increments DC_DSEL.
is filled from the cache data array on a read to DC_TAG_MSR (MSR 00001892h) or
DC_TAG_I_MSR (MSR 00001893h), and the buffer is written to the cache data array on
a write to DC_TAG_MSR or DC_TAG_I_MSR MSRs. The DC_DSEL field in the
DC_INDEX_MSR (MSR 00001890h[17:16]) selects which QWORD in the buffer is
accessed by DC_DATA, and each access to DC_DATA increments DC_DSEL.
MSR Address
00001892h
Type
R/W
Reset Value
00000000_00000000h
DC_TAG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
LRU
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TAG
RSVD
DIR
T
Y
VA
L
ID
DC_TAG_MSR Bit Descriptions
Bits
Name
Description
63:50
RSVD (RO)
Reserved (Read Only). (Default = 0)