Справочник Пользователя для AMD LX 900@1.5W
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AMD Geode™ LX Processors Data Book
GeodeLink™ Memory Controller Register Descriptions
33234H
6.2.2.12 Performance Counters (MC_CFPERF_CNT1)
2:0
WR2DAT
Write Command To Data Latency. Number of clocks between the write command
and the first data beat. Valid values are: [2,1,0], and must correspond to the installed
DIMMs as follows:
and the first data beat. Valid values are: [2,1,0], and must correspond to the installed
DIMMs as follows:
0h: No delay.
1h: 1-clock delay for DDR unbuffered DIMMs. (Default)
1h: 1-clock delay for DDR unbuffered DIMMs. (Default)
MSR Address
2000001Bh
Type
RO
Reset Value
00000000_00000000h
MC_CF1017_DATA Bit Descriptions
Bit
Name
Description
MC_CFPERF_CNT1 Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
CNT1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CNT0
MC_CFPERF_CNT1 Bit Descriptions
Bit
Name
Description
63:32
CNT0
Counter 0. Performance counter 0. Counts the occurrence of events at the GLIU inter-
face. Events are specified in CNT0_DATA (MSR 2000001Ch[7:0]). Reset and stop con-
trol on this counter is done via MSR 200001Ch[33:32]. (Default = 0h)
face. Events are specified in CNT0_DATA (MSR 2000001Ch[7:0]). Reset and stop con-
trol on this counter is done via MSR 200001Ch[33:32]. (Default = 0h)
31:0
CNT1
Counter 1. Performance counter 1. Counts the occurrence of events at the GLIU inter-
face. Events are specified in CNT1_DATA (MSR 2000001Ch[23:16]. Reset and stop con-
trol on this counter is done via MSR 200001Ch[35:34]. (Default = 0h)
face. Events are specified in CNT1_DATA (MSR 2000001Ch[23:16]. Reset and stop con-
trol on this counter is done via MSR 200001Ch[35:34]. (Default = 0h)