Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
275
Graphics Processor Register Definitions
33234H
6.4.2.23 Width/Height (GP_CH3_WIDHI)
This register is used to specify the width and the height of the bitmap to be fetched on channel 3 in pixels. This need not
match the destination width and height, as in the case of a rotation BLT where the width and height are swapped, but the
total number of pixels should be equal to the number of pixels in the destination.
match the destination width and height, as in the case of a rotation BLT where the width and height are swapped, but the
total number of pixels should be equal to the number of pixels in the destination.
6.4.2.24 Host Source (GP_CH3_HSRC)
This register is used by software to load channel 3 data when the channel 3 pattern mode bit is not set, the channel 3
enable bit is set, and the channel 3 host source bit is set.This register is also aliased to the address range 400h-FFFh
allowing the processor to load large blocks of data to the GP using the repeat MOVS instruction.
enable bit is set, and the channel 3 host source bit is set.This register is also aliased to the address range 400h-FFFh
allowing the processor to load large blocks of data to the GP using the repeat MOVS instruction.
GP Memory Offset 68h
Type
Type
R/W
Reset Value
00000000h
GP_CH3_WIDHI Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
WID
RSVD
HI
GP_CH3_WIDHI Bit Descriptions
Bit
Name
Description
31:28
RSVD
Reserved. Write as read.
27:16
WID
Width. Width in pixels of the BLT operation.
15:12
RSVD
Reserved. Write as read.
11:0
HI
Height. Height in pixels of the BLT operation.
GP Memory Offset 6Ch
Type
Type
WO
Reset Value
xxxxxxxxh
GP_CH3_HSRC Register Map
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HST_SRC
GP_CH3_HSRC Bit Descriptions
Bit
Name
Description
31:0
HST_SRC
Host Source Data. Used during BLT in host source mode