Справочник Пользователя для AMD LX 900@1.5W
310
AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6.1.5
GLD Power Management MSR (GLD_MSR_PM)
6.6.1.6
GLIU0 Device Diagnostic MSR (GLD_MSR_DIAG)
This register is reserved for internal use by AMD and should not be written to.
MSR Address
80002004h
Type
R/W
Reset Value
00000000_00000015h
GLD_MSR_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
V
G
A_GLCLK_PMODE
D
C
L
K_
PM
O
D
E
GLCLK_PMODE
GLD_MSR_PM Bit Descriptions
Bit
Name
Description
63:6
RSVD
Reserved. Set to 0.
5:4
VGA_GLCLK_
PMODE
PMODE
VGA GLIU0 Clock Power Management Mode. This field controls the internal clock
gating for the GLIU0 clock to the VGA module.
gating for the GLIU0 clock to the VGA module.
00: Clock is not gated.
01: Enable active hardware clock gating. Hardware automatically determines when it is
01: Enable active hardware clock gating. Hardware automatically determines when it is
idle, and internally disables the GLIU0 clock whenever possible.
10: Reserved.
11: Reserved.
11: Reserved.
3:2
DCLK_PMODE
Dot Clock Power Management Mode. This field controls the internal clock gating for
the Dot clock to all logic other than the VGA unit.
the Dot clock to all logic other than the VGA unit.
00: Clock is not gated.
01: Enable active hardware clock gating. Hardware automatically determines when it is
01: Enable active hardware clock gating. Hardware automatically determines when it is
idle, and internally disables the Dot clock whenever possible.
10: Reserved.
11: Reserved.
11: Reserved.
1:0
G:CLK_PMODE
GLIU0 Clock Power Management Mode. This field controls the internal clock gating
for the GLIU0 Clock to all logic other than the VGA unit.
for the GLIU0 Clock to all logic other than the VGA unit.
00: Clock is not gated.
01: Enable active hardware clock gating. Hardware automatically determines when it is
01: Enable active hardware clock gating. Hardware automatically determines when it is
idle, and internally disables the GLIU0 clock whenever possible.
10: Reserved.
11: Reserved.
11: Reserved.
MSR Address
80002005h
Type
R/W
Reset Value
00000000_00000000h