Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
343
Display Controller Register Descriptions
33234H
6.6.10.3 DC Filter Coefficient Data Register 1 (DC_FILT_COEFF1)
Any read or write of this register causes a read or write of the horizontal or filter coefficient RAM. If this occurs while the dis-
play is active, improper filtering of an output pixel can occur, which may cause temporary visual artifacts (speckling). To
avoid this, either disable the display or avoid accessing this register unless during vertical blank.
play is active, improper filtering of an output pixel can occur, which may cause temporary visual artifacts (speckling). To
avoid this, either disable the display or avoid accessing this register unless during vertical blank.
11
INTL_EN
Interlace Enable. Settings written to this field will not take effect until the start of the fol-
lowing frame or interlaced field.
lowing frame or interlaced field.
Setting this bit to 1 configures the output to interlaced mode. In this mode, the vertical
timings are based on the even timing registers for every other field. This bit must be set if
the flicker filter or address interlacing is enabled.
timings are based on the even timing registers for every other field. This bit must be set if
the flicker filter or address interlacing is enabled.
When using the VGA and interlacing, the scaler must also be used (i.e., bit 12 of this reg-
ister must be set).
ister must be set).
10
H_FILT_SEL
Horizontal Filter Select. Setting this bit to 1 allows access to the horizontal filter coeffi-
cients via this register and the Filter Data Registers (DC Memory Offset 098h and 09Ch).
When this bit is cleared, the vertical filter coefficients are accessed instead.
cients via this register and the Filter Data Registers (DC Memory Offset 098h and 09Ch).
When this bit is cleared, the vertical filter coefficients are accessed instead.
9:8
RSVD
Reserved.
7:0
FILT_ADDR
Filter Coefficient Address. This indicates which filter location is accessed through
reads and writes of the DC Filter Coefficient Data Register 1 (DC Memory Offset 098h).
reads and writes of the DC Filter Coefficient Data Register 1 (DC Memory Offset 098h).
DC Memory Offset 098h
Type
Type
R/W
Reset Value
xxxxxxxxh
DC_IRQ_FILT_CTL Bit Descriptions (Continued)
Bit
Name
Description
DC_FILT_COEFF1 Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
TAP3
TAP2
TAP1
DC_ FILT_COEFF1 Bit Descriptions
Bit
Name
Description
31:30
RSVD
Reserved. Set to 0.
29:20
TAP3
Tap 3 Coefficient. This coefficient is used for the third tap in the filter (the lower tap of
the vertical filter or the center tap of the horizontal filter). Each of the four components of
the pixel color (Red, Green, Blue, and Alpha, if available) is expanded to 8 bits and then
multiplied by this value before being summed with the weighted results of the other filter
taps.
the vertical filter or the center tap of the horizontal filter). Each of the four components of
the pixel color (Red, Green, Blue, and Alpha, if available) is expanded to 8 bits and then
multiplied by this value before being summed with the weighted results of the other filter
taps.
19:10
TAP2
Tap 2 Coefficient. This coefficient is used for the second tap in the filter (the center tap
of the vertical filter or the second tap from the left in the horizontal filter).
of the vertical filter or the second tap from the left in the horizontal filter).
9:0
TAP1
Tap 1 Coefficient. This coefficient is used for the first tap in the filter (the upper tap of the
vertical filter or the leftmost tap of the horizontal filter).
vertical filter or the leftmost tap of the horizontal filter).