Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
355
Display Controller Register Descriptions
33234H
6.6.16
VGA Block Configuration Registers
6.6.16.1 VGA Configuration (VGA_CONFIG)
This register controls palette write operations.
6.6.16.2 VGA Status (VGA_STATUS)
This register provides status information for the individual SMI events enabled in the VGA_CONFIG register (DC Memory
Offset 100h), as well as certain other status bits. Reading this register clears all active events.
Offset 100h), as well as certain other status bits. Reading this register clears all active events.
DC Memory Offset 100h
Type
Type
R/W
Reset Value
00000000h
VGA_CONFIG Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
WP
P
A
L
VGA_CONFIG Bit Descriptions
Bit
Name
Description
31:1
RSVD
Reserved. Set to 0.
0
WPPAL
Write Protect Palette. If set to 1, VGA palette write operations are NOT written to the
palette RAMs. Palette writes behave normally, except that the data is discarded.
palette RAMs. Palette writes behave normally, except that the data is discarded.
DC Memory Offset 104h
Type
Type
RO
Reset Value
00000000h
VGA_STATUS Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
BLINK_CNT
RSVD
V_CNT
RSVD
VSYNC
DISPEN
CR
T
C
IO_SMI
VBLANK_SMI
ISR0
_SMI
MISC_SMI
VGA_STATUS Bit Descriptions
Bit
Name
Description
31:30
RSVD
Reserved.
29:24
BLINK_CNT
Blink Counter Value. Unsynchronized, used as a simulation aid.
23:22
RSVD
Reserved.
21:12
V_CNT
Vertical Counter Value. Unsynchronized, used as a simulation aid.
11:6
RSVD
Reserved.
5
VSYNC
VSYNC. 1 If VSYNC is active (copy of bit 3 of ISR1).
4
DISPEN
Display Enable. 0 if both horizontal and vertical display enable are active (copy of bit 0
of ISR1).
of ISR1).
3
CRTCIO_SMI
CRTC Register SMI. If = 1, an SMI was generated due to an I/O read or write to an non-
implemented CRTC register.
implemented CRTC register.