Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
385
Display Controller Register Descriptions
33234H
6.6.23.1 ExtendedRegisterLock
6.6.23.2 ExtendedModeControl
6.6.23.3 ExtendedStartAddress
CRTC Index
030h
Type
R/W
Reset Value
FFh
ExtendedRegisterLock Register Bit Descriptions
Bit
Name
Description
7:0
LOCK
Lock. A value of 4Ch unlocks the extended registers. Any other value locks the extended
registers so they are read only. If the extended registers are currently locked, a read to
this register will return FFh. If they are unlocked, a read will return 0.
registers so they are read only. If the extended registers are currently locked, a read to
this register will return FFh. If they are unlocked, a read will return 0.
CRTC Index
043h
Type
R/W
Reset Value
00h
ExtendedModeControl Register Bit Descriptions
Bit
Name
Description
7:3
RSVD
Reserved.
2:1
VG_RG_MAP
DC Register Mapping. These bits determine the DC register visibility within the standard
VGA memory space (A0000h-BFFFFh). Note that the VGA address space control bits
override this feature. If the Miscellaneous Output register RAM Enable bit is 0, all VGA
memory space is disabled. Or, if the Memory Map bits of the Graphics Miscellaneous
register are set the same as these bits, then the VGA frame buffer memory will appear in
this space instead of the GUI registers.
VGA memory space (A0000h-BFFFFh). Note that the VGA address space control bits
override this feature. If the Miscellaneous Output register RAM Enable bit is 0, all VGA
memory space is disabled. Or, if the Memory Map bits of the Graphics Miscellaneous
register are set the same as these bits, then the VGA frame buffer memory will appear in
this space instead of the GUI registers.
00: Disabled
01: A0000h
10: B0000h
11: B8000h
01: A0000h
10: B0000h
11: B8000h
0
PACK_CH4
Packed Chain4: When this bit is set, the chain4 memory mapping will not skip DWORDs
as in true VGA. Host reads and writes to frame buffer DWORDs are contiguous. When
this bit is 0, host accesses behave normally and access 1 DWORD out of every 4. Note
that this bit has no effect on the VGA display refresh activity. This bit is only intended to
provide a front end for packed SVGA modes being displayed by DC.
as in true VGA. Host reads and writes to frame buffer DWORDs are contiguous. When
this bit is 0, host accesses behave normally and access 1 DWORD out of every 4. Note
that this bit has no effect on the VGA display refresh activity. This bit is only intended to
provide a front end for packed SVGA modes being displayed by DC.
CRTC Index
044h
Type
R/W
Reset Value
00h
ExtendedStartAddress Register Bit Descriptions
Bit
Name
Description
7:6
RSVD
Reserved.
5:0
ST_AD_RG
[21:16]
[21:16]
Start Address Register Bits [21:16]. Start Address Register Bits [23:18]: These bits
extend the VGA start address to 24 bits. Bits [17:10] are in Start Address Hi (Index 0Ch),
and bits [9:2] are in Start Address Lo (Index 0Ch).
extend the VGA start address to 24 bits. Bits [17:10] are in Start Address Hi (Index 0Ch),
and bits [9:2] are in Start Address Lo (Index 0Ch).