Справочник Пользователя для AMD LX 900@1.5W
406
AMD Geode™ LX Processors Data Book
Video Processor
33234H
6.7.7.3
FP Functional Description
The FP connects to the RGB port of the video mixer.
LCD Interface
The FP interfaces directly to industry standard 18-bit or 24-
bit active matrix thin-film-transistor (TFT). The digital RGB
or video data that is supplied by the video logic is con-
verted into a suitable format to drive a wide variety range of
panels with variable bits. The LCD interface includes dith-
ering logic to increase the apparent number of colors dis-
played for use on panels with less than 6 bits per color. The
LCD interface also supports automatic power sequence of
panel power supplies.
bit active matrix thin-film-transistor (TFT). The digital RGB
or video data that is supplied by the video logic is con-
verted into a suitable format to drive a wide variety range of
panels with variable bits. The LCD interface includes dith-
ering logic to increase the apparent number of colors dis-
played for use on panels with less than 6 bits per color. The
LCD interface also supports automatic power sequence of
panel power supplies.
Mode Selection
The FP can be configured for operation with most standard
TFT panels:
The FP can be configured for operation with most standard
TFT panels:
• Supports TFT panels with up to 24-bit interface with
640x480, 800x600, 1024x768,
1280x1024, and
1600x1200 pixel resolutions. Either one or two pixels per
clock is supported for all resolutions. Other resolutions
below 640x480 are also supported.
clock is supported for all resolutions. Other resolutions
below 640x480 are also supported.
Table 6-66 shows the mapping of the data in the supported
modes.
modes.
For TFT panel support, the output from the dither block is
directly fed on to the panel data pins (DRGBx). The data
that is being sent on to the panel data pins is in sync with
the TFT timing signals such as HSYNC, VSYNC, and LDE.
One pixel (or two pixels in 2 pix/clk mode) is shifted on
every positive edge of the clock as long as DISP_ENA is
active.
directly fed on to the panel data pins (DRGBx). The data
that is being sent on to the panel data pins is in sync with
the TFT timing signals such as HSYNC, VSYNC, and LDE.
One pixel (or two pixels in 2 pix/clk mode) is shifted on
every positive edge of the clock as long as DISP_ENA is
active.
Table 6-66. Panel Output Signal Mapping
Pin Name
TFT
9-Bit
TFT
18-Bit
TFT
24-Bit
TFT
9+9-Bit
TFT
12+12-Bit
DRGB0
B0
BB0
DRGB1
B1
BB0
BB1
DRGB2
B0
B2
BB1
BB2
DRGB3
B1
B3
BB2
BB3
DRGB4
B2
B4
GB0
DRGB5
B0
B3
B5
GB0
GB1
DRGB6
B1
B4
B6
GB1
GB2
DRGB7
B2
B5
B7
GB2
GB3
DRGB8
G0
RB0
DRGB9
G1
RB0
RB1
DRGB10
G0
G2
RB1
RB2
DRGB11
G1
G3
RB2
RB3
DRGB12
G2
G4
BA0
DRGB13
G0
G3
G5
BA0
BA1
DRGB14
G1
G4
G6
BA1
BA2
DRGB15
G2
G5
G7
BA2
BA3
DRGB16
R0
GA0
DRGB17
R1
GA0
GA1
DRGB18
R0
R2
GA1
GA2
DRGB19
R1
R3
GA2
GA3
DRGB20
R2
R4
RA0
DRGB21
R0
R3
R5
RA0
RA1
DRGB22
R1
R4
R6
RA1
RA2
DRGB23
R2
R5
R7
RA2
RA3