Справочник Пользователя для AMD LX 900@1.5W
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AMD Geode™ LX Processors Data Book
Video Processor Register Descriptions
33234H
6.8.3.6
Video Color Key Register (VCK)
30
GB (RO)
GLIU Behind (Read Only). This bit set indicates the GLIU line buffer fill is falling behind
the Dot display. This bit clears on read.
the Dot display. This bit clears on read.
This bit is typically set if during vertical downscale, the 2nd line buffer fill has not com-
pleted before the Dot display has started. This does not necessarily indicate an error,
recovery is possible.
pleted before the Dot display has started. This does not necessarily indicate an error,
recovery is possible.
29:16
RSVD
Reserved.
15
SP
Spare. Bit is R/W but has no function.
14
DHD
Double Horizontal Downscale. Selects which method data gets written into line buffers.
0: Write data from video interface directly.
1: Write data from video interface averaged each 2 pixels.
This bit should only be set when horizontal downscale greater than 4:1 is desired.
13
COED
Coefficient Mode. Selects between 128 and 256 coefficient usage.
0: Use common 256 vert/horz coefficient table.
1: Use separate 128 vert/horz coefficient tables.
When using separate tables, the vertical coefficient should be placed in the lower half of
the coefficient RAM (0-127 = vertical 128-255 = horizontal).
the coefficient RAM (0-127 = vertical 128-255 = horizontal).
12
LPS
Last Pixel Select. Selects method to choose last pixel for the scaler to use.
0: Use video source line size.
1: Use video window size.
The preferred setting is 0. This will avoid unnecessary horizontal mirroring.
11
SP
Spare. Bit is R/W but has no function.
10:0
VSL
Video Source Lines. Represents the total number of video source lines. For example, a
720x480 video image would have VSL = 480.
720x480 video image would have VSL = 480.
VP Memory Offset 028h
Type
Type
R/W
Reset Value
00000000_00000000h
SCL Bit Descriptions
Bit
Name
Description
VCK Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
VID_CLR_KEY
VCK Bit Descriptions
Bit
Name
Description
63:24
RSVD (RO)
Reserved (Read Only). Reads back as 0.