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AMD Geode™ LX Processors Data Book
503
Video Input Port Register Descriptions
33234H
6.10.2.20 VIP Task B V Offset (VIP_TASK_B_V_Offset)
27:16
VERTICAL_
END_EVEN
END_EVEN
(even/second
field)
field)
Vertical End Even. This register is redefined in BT.601 mode. In BT.601 type input
modes timing is derived from the external HSYNC and VSYNC inputs. This value speci-
fies the last line of the even field captured in interlaced modes. This value is ignored
when the NI bit (VIP Memory Offset 00h[19]) is set (indicating non-interlaced input). The
VERT_END (VIP Memory Offset 6Ch[27:16]) value is used for non-interlaced modes.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 473 for additional detail.
modes timing is derived from the external HSYNC and VSYNC inputs. This value speci-
fies the last line of the even field captured in interlaced modes. This value is ignored
when the NI bit (VIP Memory Offset 00h[19]) is set (indicating non-interlaced input). The
VERT_END (VIP Memory Offset 6Ch[27:16]) value is used for non-interlaced modes.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 473 for additional detail.
15:0
TASK_B_DATA
_PITCH
_PITCH
Task B Data Pitch/. Specifies the logical width of the video data buffer. This value is
added to the start of the line address to get the address of the next line where captured
video data will be stored. The value in this register needs to be 32-byte aligned in linear
mode, and 64-byte aligned in planar mode. (In linear mode, bits [4:0] are required to be
00000. In planar mode, bits [5:0] are required to be 000000.)
added to the start of the line address to get the address of the next line where captured
video data will be stored. The value in this register needs to be 32-byte aligned in linear
mode, and 64-byte aligned in planar mode. (In linear mode, bits [4:0] are required to be
00000. In planar mode, bits [5:0] are required to be 000000.)
11:0
VERT_START_
EVEN
EVEN
(even/second
field)
field)
Vertical Start Even. This register is redefined in BT.601 mode. In BT.601 type input
modes, timing is derived from the external HSYNC and VSYNC inputs. This value speci-
fies the line that the even field video data begins. Even field video data is captured until
Vertical End Even This value is ignored when the NI bit (VIP Memory Offset 00h[19]) is
set (indicating non-interlaced input). The VERT_START (VIP Memory Offset 6Ch) value
is used for non-interlaced modes. See Figure 6-48 "BT.601 Mode Vertical Timing" on
page 473 for additional detail.
modes, timing is derived from the external HSYNC and VSYNC inputs. This value speci-
fies the line that the even field video data begins. Even field video data is captured until
Vertical End Even This value is ignored when the NI bit (VIP Memory Offset 00h[19]) is
set (indicating non-interlaced input). The VERT_START (VIP Memory Offset 6Ch) value
is used for non-interlaced modes. See Figure 6-48 "BT.601 Mode Vertical Timing" on
page 473 for additional detail.
VIP Memory Offset 50h
Type
Type
R/W
Reset Value
00000000h
VIP_TASK_B_DATA_PITCH_VERT_START_EVEN BIT Descriptions (Continued)
Bit
Name
Description
VIP_TASK_B_V_OFFSET Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TASK_B_V_OFFSET_START_ODD
VIP_TAS_B_V_OFFSET Bit Descriptions
Bit
Name
Description
31:0
TASK_B_V_
OFFSET
OFFSET
Task B V Offset. This register determines the starting address of the V buffer when data
is stored in planar format. The start of the V buffer is determined by adding the contents
of this register to that of the base address. The value in this register needs to be 32-byte
aligned. (Bits [4:0] are required to be 00000.)
is stored in planar format. The start of the V buffer is determined by adding the contents
of this register to that of the base address. The value in this register needs to be 32-byte
aligned. (Bits [4:0] are required to be 00000.)
Note:
This register in NOT double buffered and should be initialized before start of
video capture.
video capture.
11:0
23:16
START_ODD
Start Odd Field Detect/Duration. This register is redefined in BT.601 mode. When in
BT.601 interlaced mode, this register determines the window for field detection. The Start
bits [11:0] are the number of clocks from the leading edge of HSYNC to when the detec-
tion window begins, the duration bits [23:16] are the # of clocks that the detection window
is active. If the leading edge of VSYNC occurs within the window, the field is set to odd,
otherwise it is set to even. At the default state of 0, the leading edge of VBLANK must
transition simultaneously with the leading edge of HSYNC for odd field detection. When
the NI bit in (VIP Memory Offset 00h[19]) is set (non-interlaced mode), all frames are
considered to be odd fields.
BT.601 interlaced mode, this register determines the window for field detection. The Start
bits [11:0] are the number of clocks from the leading edge of HSYNC to when the detec-
tion window begins, the duration bits [23:16] are the # of clocks that the detection window
is active. If the leading edge of VSYNC occurs within the window, the field is set to odd,
otherwise it is set to even. At the default state of 0, the leading edge of VBLANK must
transition simultaneously with the leading edge of HSYNC for odd field detection. When
the NI bit in (VIP Memory Offset 00h[19]) is set (non-interlaced mode), all frames are
considered to be odd fields.