Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
549
GeodeLink™ Control Processor Register Descriptions
33234H
6.14.2.7 GLCP DOWSER (GLCP_DOWSER)
6.14.2.8 GLCP I/O Delay Controls (GLCP_DELAY_CONTROLS)
MSR Address
4C00000Eh
Type
R/W
Reset Value
00000000_00000000h
GLCP_DOWSER Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
SW Defined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SW Defined
GLCP_DOWSER Bit Descriptions
Bit
Name
Description
63:0
---
Software Defined. This 64-bit scratchpad register was specifically added for SW
debugger use (DOWSER). The register resets to zero with both hard and soft resets.
debugger use (DOWSER). The register resets to zero with both hard and soft resets.
MSR Address
4C00000Fh
Type
R/W
Reset Value
00000000_00000000h
GLCP_DELAY_CONTROLS Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
EN
B_DQ
B_C
M
D
B_MA
SDCLK_SET
DDR_R
L
E
SDC
L
K_DIS
T
L
A1_O
A
D_
TLA1
D_
TLA0
D_D
Q
_E
D_DQ_O
RSVD
D
_
SDCLK
D_CMD
_
O
D_
CMD_E
D_MA_O
D_MA_E
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
D_PCI_O
D_
P
C
I_E
D_D
O
TC
LK
D
_
DRGB_O
D_DR
GB_E
D_PCI_
IN
D_T
D
BGI
D_
V
IP
D_VIPCLK
H_SDCLK
PLL_FD
_
DEL
RSVD
DLL_O
V
D
LL_O
VS/RSD
A
GLCP_DELAY_CONTROLS Bit Definition
Bit
Name
Description
63
EN
0: Use default values.
1: Use value in bits [62:0].
1: Use value in bits [62:0].
62
B_DQ
Buffer Control for DQ[63:0], DQS[7:0], DQM[7:0], TLA[1:0] drive select.
1: Half power.
0: Quarter power.
0: Quarter power.
61
B_CMD
Buffer Control for RAS[1:0]#, CAS[1:0]#, CKE[1:0], CS[3:0]#, WE[1:0]# drive select.
1: Half power.
0: Quarter power.
0: Quarter power.
60
B_MA
Buffer Control for MA[13:0] and BA[1:0].
0: Half power.
1: Full power.
1: Full power.