Справочник Пользователя для AMD LX 900@1.5W
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AMD Geode™ LX Processors Data Book
GeodeLink™ PCI Bridge Register Descriptions
33234H
6.16.2.3 GLPCI VPH / PCI Configuration Cycle Control (GLPCI_PBUS)
The PBUS model specific register is used to control the way that the GLPCI module generates (or does not generate) PCI
configuration cycles onto the PCI bus. SEC (bits [39:32]) should be configured with the PCI bus number for the locally
attached PCI bus. SUB (bits [55:48]) should be configured with the PCI bus number for the highest numbered PCI bus that
is accessible via the PCI interface. DEV (bits [31:0]) should be configured to indicate which device numbers will NOT gener-
ate PCI configuration cycles on the PCI bus.
configuration cycles onto the PCI bus. SEC (bits [39:32]) should be configured with the PCI bus number for the locally
attached PCI bus. SUB (bits [55:48]) should be configured with the PCI bus number for the highest numbered PCI bus that
is accessible via the PCI interface. DEV (bits [31:0]) should be configured to indicate which device numbers will NOT gener-
ate PCI configuration cycles on the PCI bus.
6.16.2.4 GLPCI Debug Packet Configuration (GLPCI_DEBUG)
Control relay of debug packets to PCI. The functionality that this register controls has been removed from the GLIU. There-
fore this register is obsolete.
fore this register is obsolete.
6.16.2.5 GLPCI Fixed Region Enables (GLPCI_REN)
MSR Address
50002012h
Type
R/W
Reset Value
00FF0000_00000000h
GLPCI_PBUS Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
SUB
RSVD
SEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DEV
GLPCI_PBUS Bit Descriptions
Bit
Name
Description
63:56
RSVD (RO)
Reserved (Read Only). Reserved for future use.
55:48
SUB
Subordinate Bus Number. Specifies the subordinate PCI bus number for all PCI buses
reachable via the PCI interface.
reachable via the PCI interface.
47:40
RSVD (RO)
Reserved (Read Only). Reserved for future use.
39:32
SEC
Secondary Bus Number. Specifies the secondary PCI bus number for the PCI interface.
31:0
DEV
Device Bitmap. Specifies the virtualized PCI devices. Each bit position corresponds to a
device number. A 0 instructs the GLPCI to allow PCI configuration cycles for the device
to be generated on the PCI bus. A 1 tells the GLPCI to virtualize the device by generating
an SSMI instead of a PCI configuration cycle.
device number. A 0 instructs the GLPCI to allow PCI configuration cycles for the device
to be generated on the PCI bus. A 1 tells the GLPCI to virtualize the device by generating
an SSMI instead of a PCI configuration cycle.
MSR Address
50002013h
Type
R/W
Reset Value
00000000_00000000h
MSR Address
50002014h
Type
R/W
Reset Value
00000000_00000000h
GLPCI_REN Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Spare
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
FC
F8
F4
F0
EC
E8
E4
E0
DC
D8
D4
D0
CC
C8
C4
C0
BC
B8
B4
B0
AC
A8
A4
A0