Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
73
GLIU Register Descriptions
33234H
4.2.3.3
Statistic Action (STATISTIC_ACTION[0:3]
Descriptor Statistic Action (STATISTIC_ACTION[0])
Descriptor Statistic Action (STATISTIC_ACTION[1])
Descriptor Statistic Action (STATISTIC_ACTION[2])
Descriptor Statistic Action (STATISTIC_ACTION[3])
MSR Address
GLIU0: 100000A2h
GLIU1: 400000A2h
GLIU1: 400000A2h
Type
R/W
Reset Value
00000000_00000000h
MSR Address
GLIU0: 100000A6h
GLIU1: 400000A6h
GLIU1: 400000A6h
Type
R/W
Reset Value
00000000_00000000h
MSR Address
GLIU0: 100000AAh
GLIU1: 400000AAh
GLIU1: 400000AAh
Type
R/W
Reset Value
00000000_00000000h
MSR Address
GLIU0: 100000AEh
GLIU1: 400000AEh
GLIU1: 400000AEh
Type
R/W
Reset Value
00000000_00000000h
STATISTIC_ACTION[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
PREDIV
WRAP
ZER
O
_AERR
ZXER
O_ASMI
AL
W
A
YS_DEC
HIT_AERR
H
IT_ASMI
HIT_D
E
C
HIT_LD
EN
STATISTIC_ACTION[0:3] Bit Descriptions
Bit
Name
Description
63:24
RSVD
Reserved.
23:8
PREDIV
Pre Divider. Used if ALWAYS_DEC (bit 4) is set. The predivider is free running and
extends the depth of the counter.
extends the depth of the counter.
7
WRAP
Decrement Counter Beyond Zero and Wrap.
0: Disable wrap; counter stops when it reaches zero.
1: Enable wrap; counter decrements through 0 to all ones.
1: Enable wrap; counter decrements through 0 to all ones.
6
ZERO_AERR
Assert AERR on cnt = 0. Assert AERR when STATISTIC_CNT[x] reaches 0.
0: Disable.
1: Enable.
1: Enable.
5
ZERO_ASMI
Assert ASMI on cnt = 0. Assert ASMI when STATISTIC_CNT[x] reaches 0.
0: Disable.
1: Enable.
1: Enable.
4
ALWAYS_DEC
Always Decrement Counter. If enabled, the counter decrements on every memory
clock subject to the prescaler value PREDIV (bits [23:8]). Decrementing continues unless
loading is occurring due to another action, or if the counter reaches zero and WRAP is
disabled (bit 7).
clock subject to the prescaler value PREDIV (bits [23:8]). Decrementing continues unless
loading is occurring due to another action, or if the counter reaches zero and WRAP is
disabled (bit 7).
0: Disable.
1: Enable
1: Enable
3
HIT_AERR
Assert AERR on Descirptor Hit. The descriptor hits are ANDed with the masks and
then all ORed together.
then all ORed together.
0: Disable.
1: Enable
1: Enable