Справочник Пользователя для AMD LX 900@1.5W
94
AMD Geode™ LX Processors Data Book
CPU Core
33234H
5.4
System Register Set
The System Register Set, shown in Table 5-5, consists of
registers not generally used by application programmers.
These registers are either initialized by the system BIOS or
employed by system level programmers who generate
operating systems and memory management programs.
Associated with the System Register Set are certain tables
and registers that are listed in Table 5-5.
registers not generally used by application programmers.
These registers are either initialized by the system BIOS or
employed by system level programmers who generate
operating systems and memory management programs.
Associated with the System Register Set are certain tables
and registers that are listed in Table 5-5.
The Control registers control certain aspects of the CPU
Core such as paging, coprocessor functions, and segment
protection.
Core such as paging, coprocessor functions, and segment
protection.
The CPU Core Configuration registers are used to initial-
ize, provide for, test or define most of the features of the
CPU Core. The attributes of these registers include:
ize, provide for, test or define most of the features of the
CPU Core. The attributes of these registers include:
• CPU setup - Enable cache, features, operating modes.
• Debug support - Provide debugging facilities for the
Geode™ LX processor and enable the use of data
access breakpoints and code execution breakpoints.
access breakpoints and code execution breakpoints.
• Built-in Self-test (BIST) support.
• Test - Support a mechanism to test the contents of the
on-chip caches and the Translation Lookaside Buffers
(TLBs).
(TLBs).
• In-Circuit Emulation (ICE) - Provide for a alternative
accessing path to support an ICE.
• CPU identification - Allow the BIOS and other software
to identify the specific CPU and stepping.
• Power Management.
• Performance Monitoring - Enables test software to
measure the performance of application software.
The Descriptor Table registers point to tables used to
manage memory segments and interrupts.
manage memory segments and interrupts.
The Task State register points to the Task State Segment,
which is used to save and load the processor state when
switching tasks.
which is used to save and load the processor state when
switching tasks.
Table 5-5 lists the System Register Sets along with their
size and function.
size and function.
Table 5-5. System Register Set
Group
Name
Function
Width
(Bits)
Control
Registers
Registers
CR0
System Control
Register
Register
32
CR2
Page Fault Linear
Address Register
Address Register
32
CR3
Page Directory Base
Register
Register
32
CR4
Feature Enables
32
CPU Core
Configuration
Registers
Configuration
Registers
PLn
Pipeline
Control Registers
Control Registers
64
IMn
Instruction Memory
Control Registers
Control Registers
64
DMn
Data Memory Con-
trol Registers
trol Registers
64
BCn
Bus Controller Con-
trol Registers
trol Registers
64
FPUn
Floating Point Unit
Shadow Registers
Shadow Registers
64
Descriptor
Table
Registers
Table
Registers
GDTR
GDT Register
32
IDTR
IDT Register
32
LDTR
LDT Register
16
Task Register
TR
Task Register
16
Performance
Registers
Registers
PCRn
Performance
Control Registers
Control Registers
8