Справочник Пользователя для AMD LX 800@0.9W
122
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.13 IF Sequential Count MRS (IF_SEQCOUNT_MSR)
IF SEQCOUNT MSR is a read only MSR containing the number of sequential instructions executed since the last change of
flow. This is useful when the CPU is halted, since it helps determine the instructions executed since the last record of the
BTM stream.
flow. This is useful when the CPU is halted, since it helps determine the instructions executed since the last record of the
BTM stream.
IF_TEST_DATA_MSR Register Map for Return Stack Valids
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
ID_SPEC_VLD
IF_SPEC_VLD[7:0]
NONSPEC_VLD[7:0]
IF_TEST_DATA_MSR Bit Descriptions for Return Stack Valids
Bit
Name Description
63:24
RSVD
Reserved.
23:16
ID_SPEC_VLD
Valid Instruction Decode Speculative. ID speculative return stack entries that are
valid. The lease significant entry is the next to be popped from the stack. (Default = 0)
valid. The lease significant entry is the next to be popped from the stack. (Default = 0)
15:8
IF_SPEC_VLD
Valid Instruction Fetch Speculative. IF speculative return stack entries that are valid.
The least significant entry is the next to be popped from the stack. (Default = 0)
The least significant entry is the next to be popped from the stack. (Default = 0)
7:0
NONSPEC_VLD
Valid Non-Speculative. Non-speculative return stack entries that are valid. The least
significant entry the next to be popped from the stack. (Default = 0)
significant entry the next to be popped from the stack. (Default = 0)
MSR Address
00001110h
Type
RO
Reset Value
00000000_00000000h
IF_SEQCOUNT_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
SEQCOUNT
IF_SEQCOUNT_MSR Bit Descriptions
Bit
Name Description
63:5
RSVD
Reserved.
4:0
SEQCOUNT
Sequential Count. Number of sequential instructions executed since the last change of
flow.
flow.