Справочник Пользователя для AMD LX 800@0.9W
AMD Geode™ LX Processors Data Book
185
CPU Core Register Descriptions
33234H
5.5.2.91 Reserved Status MSR (RSVD_STS_MSR)
5.5.2.92 MSR Lock MSR (MSR_LOCK_MSR)
MSR Address
00001904h
Type
RO
Reset Value
00000000_00000000h
RSVD_STS_MSR Bit Descriptions
Bit
Name
Description
63:0
RSVD (RO)
Reserved (Read Only). Reads back as 0.
MSR Address
00001908h
Type
R/W
Reset Value
00000000_00000000h
MSR_LOCK_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
MSR_LOCK
MSR_LOCK_MSR Bit Descriptions
Bit
Name
Description
63:1
RSVD
Reserved. Write as read
0
MSR_LOCK
Lock MSRs. The CPU Core MSRs above 0xFFF (with the exception of the MSR_LOCK
register itself) are locked when this bit reads back as 1. To unlock these MSRs, write the
value 45524F434C494156h to this register. Writing any other value locks the MSRs.
register itself) are locked when this bit reads back as 1. To unlock these MSRs, write the
value 45524F434C494156h to this register. Writing any other value locks the MSRs.
The lock only affects software access via the WRMSR and RDMSR instructions when the
processor is NOT in SMM or DMM mode. MSRs are always writable and readable from
the GLBus and when the processor is in SMM or DMM mode regardless of the state of
the LOCK bit.
processor is NOT in SMM or DMM mode. MSRs are always writable and readable from
the GLBus and when the processor is in SMM or DMM mode regardless of the state of
the LOCK bit.
Note that a write or read to a locked MSR register causes a protection exception in the
pipeline.
pipeline.
When MSRs are locked, no GLBus MSR transactions are generated (GLBus MSR
addresses are above 3FFFh).
addresses are above 3FFFh).