Справочник Пользователя для AMD LX 800@0.9W
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AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6
Display Controller Register Descriptions
This section provides information on the registers associ-
ated with the Display Controller (DC) (i.e., GUI and VGA
blocks), including the Standard GeodeLink™ Device (GLD)
MSRs and the Display Controller Specific MSRs (accessed
via the RDMSR and WRMSR instructions). Table 6-45
through Table 6-50 are register summary tables that
ated with the Display Controller (DC) (i.e., GUI and VGA
blocks), including the Standard GeodeLink™ Device (GLD)
MSRs and the Display Controller Specific MSRs (accessed
via the RDMSR and WRMSR instructions). Table 6-45
through Table 6-50 are register summary tables that
include reset values and page references where the bit
descriptions are provided.
descriptions are provided.
Note:
The MSR address is derived from the perspective
of the CPU Core. See Section 4.1 "MSR Set" on
page 45 for more details on MSR addressing.
of the CPU Core. See Section 4.1 "MSR Set" on
page 45 for more details on MSR addressing.
Table 6-45. Standard GeodeLink™ Device MSRs Summary
MSR
Address
Type
Register Name
Reset Value
Reference
Table 6-46. DC Specific MSRs Summary
MSR
Address
Type
Register Name
Reset Value
Reference
Table 6-47. DC Configuration Control Register Summary
DC
Memory
Offset
Type
Register Name
Reset Value
Reference
Configuration and Status Registers
Memory Organization Registers