Справочник Пользователя для AMD LX 800@0.9W
378
AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6.20.10 VGA Color Don’t Care
6.6.20.11 VGA Bit Mask
6.6.21
Attribute Controller Registers
The attribute controller registers are accessed by writing an index value to the Attribute Controller Index register (3C0h) and
reading or writing the register using the Attribute Controller Data register (3C0h for writes, 3C1h for reads).
reading or writing the register using the Attribute Controller Data register (3C0h for writes, 3C1h for reads).
Index
07h
Type
R/W
Reset Value
xxh
VGA Color Don’t Care Register Bit Descriptions
Bit
Name
Description
7:4
RSVD
Reserved.
3
CM_PR3
Compare Map 3. This bit enables (bit = 1) or excludes (bit = 0) map 3 from participating
in a color compare operation.
in a color compare operation.
2
CM_PR2
Compare Map 2. This bit enables (bit = 1) or excludes (bit = 0) map 2 from participating
in a color compare operation.
in a color compare operation.
1
CM_PR1
Compare Map 1. This bit enables (bit = 1) or excludes (bit = 0) map 1 from participating
in a color compare operation.
in a color compare operation.
0
CM_PR0
Compare Map 0. This bit enables (bit = 1) or excludes (bit = 0) map 0 from participating
in a color compare operation.
in a color compare operation.
Index
08h
Type
R/W
Reset Value
xxh
VGA Bit Mask Register Bit Descriptions
Bit
Name
Description
7:0
BT_MSK
Bit Mask. The bit mask is used to enable or disable writing to individual bits in each map.
A 1 in the bit mask allows a bit to be updated, while a 0 in the bit mask writes the contents
of the data latches back to memory, effectively protecting that bit from update. The data
latches must be set by doing a frame buffer read in order for the masking operation to
work properly. The bit mask is used in write modes 0, 2, and 3.
A 1 in the bit mask allows a bit to be updated, while a 0 in the bit mask writes the contents
of the data latches back to memory, effectively protecting that bit from update. The data
latches must be set by doing a frame buffer read in order for the masking operation to
work properly. The bit mask is used in write modes 0, 2, and 3.
Table 6-57. Attribute Controller Registers Summary
Index
Type
Register
Reset Value
Reference
--
xxh
xxh
xxh
xxh
xxh
xxh
R/W
xxh