Справочник Пользователя для AMD LX 800@0.9W
386
AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6.23.4 WriteMemoryAperture
6.6.23.5 ReadMemoryAperture
6.6.23.6 BlinkCounterCtl
This register is for simulation and test only.
CRTC Index
047h
Type
R/W
Reset Value
00h
WriteMemoryAperture Register Bit Descriptions
Bit
Name
Description
7:0
WR_BASE
WriteBase. Offset added to the graphics memory base to specify where VGA write oper-
ations start. This value provides DWORD address bits [21:14] when mapping host VGA
writes to graphics memory. This allows the VGA base address to start on any 64 KB
boundary within the 8 MB of graphics memory.
ations start. This value provides DWORD address bits [21:14] when mapping host VGA
writes to graphics memory. This allows the VGA base address to start on any 64 KB
boundary within the 8 MB of graphics memory.
CRTC Index
048h
Type
R/W
Reset Value
00h
ReadMemoryAperture Register Bit Descriptions
Bit
Name
Description
7:0
RD_BASE
ReadBase. Offset added to the graphics memory base to specify where VGA read oper-
ations start. This value provides DWORD address bits [21:14] when mapping host VGA
reads to graphics memory. This allows the VGA base address to start on any 64 KB
boundary within the 8 MB of graphics memory.
ations start. This value provides DWORD address bits [21:14] when mapping host VGA
reads to graphics memory. This allows the VGA base address to start on any 64 KB
boundary within the 8 MB of graphics memory.
CRTC Index
060h
Type
R/W
Reset Value
00h
BlinkCounterCtl Register Bit Descriptions
Bit
Name
Description
7
HLD_CNT
Hold Count. When set, prevents the blink counter from incrementing with each leading
edge VSYNC.
edge VSYNC.
6:5
RSVD
Reserved.
4:0
BLNK_CNT
Blink Count. The blink counter is loaded with this value while the Sequencer Reset reg-
ister is in the reset state.
ister is in the reset state.