Справочник Пользователя для AMD LX 800@0.9W

AMD Geode™ LX Processors Data Book

405

Video Processor

33234H

6.7.7

Flat Panel Display Controller

6.7.7.1

FP Functional Overview

The flat panel (FP) display controller converts the digital
RGB output of the Video Mixer block to digital output suit-
able for driving a TFT flat panel LCD.

Features include:

• 24-bit color support for digital pixel input.

• 170 MHz pixel clock operation supports up to

1600x1200 TFT panels.

• Supports most SVGA TFT panels and the VESA FPDI

(Flat Panel Display Interface) Revision 1.0 Specification.

• TFT panel support provided by use of one connector

allows a pass-through mode for the digital pixel input.

• 9-, 12-, 18-, and 24-bit 1 pixel per clock TFT support.

• 9+9 or 12+12-bit, and 24-bit 2 pixels per clock TFT panel

support.

• Programmable dither, up to 64 levels.

6.7.7.2

FP Architecture Overview

The FP display controller contains the following functional
blocks, as shown in Figure 6-36:

• Dither Engine

• Control Registers

• TFT Timing Generator

• Panel Interface

• CRC (Cyclical Redundancy Check) Engine

Figure 6-36. Flat Panel Display Controller Block Diagram

Dither

Pixel

Panel

Control Registers

Control

Data

Control

Data

Engine

TFT Timing

Generator

Panel

Interface

CRC

Engine