Справочник Пользователя для AMD LX 800@0.9W
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AMD Geode™ LX Processors Data Book
Video Processor Register Descriptions
33234H
6.8.2.2
Pad Select MSR (MSR_PADSEL)
MSR Address
48002011h
Type
R/W
Reset Value
00000000_00000000h
MSR_PADSEL Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
VO
P
C
IN
V
RS
V
D
DF_DRGB[31:26]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DF_D
RGB[2
5
:24]
RSVD
DF
_DCLK
DF_
D
ISP_EN
D
F
_LDE
D
F
_VSYNC
DF_H
SY
N
C
DF_DRGB[23:0]
MSR_PADSEL Bit Descriptions
Bit
Name
Description
63:40
RSVD
Reserved.
39
VOPCINV
Invert VOP Clock. This is used to invert the VOP output clock. This may be used to meet
system timing requirements.
system timing requirements.
0: Non-inverted.
1: Inverted.
1: Inverted.
38
RSVD
Reserved.
37:0
PADS
Select for Registered or Non-Registered VP Outputs. Bits select whether to use the
registers in the pad logic. The reset value of 38’b0 is valid for TFT 2 pixel per clock and
CRT mode.
registers in the pad logic. The reset value of 38’b0 is valid for TFT 2 pixel per clock and
CRT mode.
Bits [37:30]: DF_DRGB[31:24]
0: Registered output.
1: Direct output.
0: Registered output.
1: Direct output.
Bit 29: RSVD.
Always write 0.
Always write 0.
Bit 28: DF_DCLK
Bit 27: DF_DISP_EN
Bit 26: DF_LDE
Bit 25: DF_VSYNC
Bit 24: DF_HSYNC
Bits [23:0]: DF_DRGB[23:0]
0: Registered output.
1: Direct output.
Bit 27: DF_DISP_EN
Bit 26: DF_LDE
Bit 25: DF_VSYNC
Bit 24: DF_HSYNC
Bits [23:0]: DF_DRGB[23:0]
0: Registered output.
1: Direct output.