Справочник Пользователя для AMD LX 800@0.9W
544
AMD Geode™ LX Processors Data Book
GeodeLink™ Control Processor Register Descriptions
33234H
6.14.1.5 GLD Power Management MSR (GLD_MSR_PM)
The debug logic powers up selecting GLIU1 for its clock. Debug clock select is in GLCP_DBGCLKCTL (MSR
4C000016h[2:0]).
4C000016h[2:0]).
6.14.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
This register is reserved for internal use by AMD and should not be written to.
MSR Address
4C002004h
Type
R/W
Reset Value
00000000_00000015h
GLD_MSR_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
PM_PCI
PM_DBG
PM_GLIU
GLD_MSR_PM Bit Descriptions
Bit
Name
Description
63:32
RSVD
Reserved. Write as read.
31:6
RSVD
Reserved. Write as 0.
5:4
PM_PCI
GLCP PCI Clock Power Mode.
00: Clock always on.
01: Hardware clock gating (GIO interface will wake instantly when SUSP goes low).
1x: Reserved.
01: Hardware clock gating (GIO interface will wake instantly when SUSP goes low).
1x: Reserved.
3:2
PM_DBG
GLCP Debug Clock Power Mode.
00: Clock always on.
01: Hardware clock gating if debug inactive (if GLCP_DBGCLKCTL = 0).
1x: Reserved.
01: Hardware clock gating if debug inactive (if GLCP_DBGCLKCTL = 0).
1x: Reserved.
1:0
PM_GLIU
GLCP GLIU Clock Power Mode.
00: Clock always on.
01: Hardware clock gating if GLCP inactive.
1x: Reserved.
01: Hardware clock gating if GLCP inactive.
1x: Reserved.
MSR Address
4C002005h
Type
R/W
Reset Value
00000000_00000000h