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AMD Geode™ LX Processors Data Book
GeodeLink™ PCI Bridge Register Descriptions
33234H
6.16
GeodeLink™ PCI Bridge Register Descriptions
All GeodeLink™ PCI Bridge (GLPCI) registers are Model
Specific Registers (MSRs) and are accessed via the
RDMSR and WRMSR instructions.
Specific Registers (MSRs) and are accessed via the
RDMSR and WRMSR instructions.
The registers associated with the GLPCI are the Standard
GeodeLink Device (GLD) MSRs and GLPCI Specific
MSRs. Table 6-91 and Table 6-92 are register summary
GeodeLink Device (GLD) MSRs and GLPCI Specific
MSRs. Table 6-91 and Table 6-92 are register summary
tables that include reset values and page references where
the bit descriptions are provided.
the bit descriptions are provided.
The MSR address is derived from the perspective of the
CPU Core. See Section 4.1 "MSR Set" on page 45 for
more detail on MSR addressing.
CPU Core. See Section 4.1 "MSR Set" on page 45 for
more detail on MSR addressing.
Table 6-91. Standard GeodeLink™ Device MSRs Summary
MSR
Address
Type
Register Name
Reset Value
Reference
Table 6-92. GLPCI Specific Registers Summary
MSR
Address
Type
Register Name
Reset Value
Reference