Справочник Пользователя для AMD LX 800@0.9W
576
AMD Geode™ LX Processors Data Book
GeodeLink™ PCI Bridge Register Descriptions
33234H
6.16.1.4 GLD Error MSR (GLD_MSR_ERROR)
MSR Address
MSR Address
50002003h
Type
R/W
Reset Value
00000000_0000003Fh
GLD_MSR_ERROR Register Map
63 62 61 60 59 58 57 56 55 54 53
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
PA
R
E
SYSE
RSVD
BME
TA
R
E
MARE
RSVD
PA
R
M
SYSM
RSVD
BMM
TA
R
M
MA
R
M
GLD_MSR_ERROR Bit Descriptions
Bit
Name
Description
63:22
RSVD (RO)
Reserved (Read Only). Reserved for future use.
21
PARE
Parity Error Event (Read/Write-1-to-Clear). This bit is asserted due to detection of a
PCI bus parity error. Write 1 to clear. PE (MSR 50002010h[31]) must be set to enable this
event. The event causes an ERR if PARM (bit 5) is cleared.
PCI bus parity error. Write 1 to clear. PE (MSR 50002010h[31]) must be set to enable this
event. The event causes an ERR if PARM (bit 5) is cleared.
20
SYSE
System Error Event (Read/Write-1-to-Clear). This bit is asserted due to the detection
of a PCI bus system error. Write 1 to clear. PE (MSR 50002010h[31]) must be set to
enable this event. The event causes an ERR if SYSM (bit 4) is cleared.
of a PCI bus system error. Write 1 to clear. PE (MSR 50002010h[31]) must be set to
enable this event. The event causes an ERR if SYSM (bit 4) is cleared.
19
RSVD (RO)
Reserved (Read Only). Reserved for future use.
18
BME
Broken Master Event (Read/Write-1-to-Clear). This bit is asserted due to detection of a
broken PCI bus master. Write 1 to clear. BME (MSR 50002010h[30]) must be set to
enable this event. The event causes an ERR if BMM (bit 2) is cleared.
broken PCI bus master. Write 1 to clear. BME (MSR 50002010h[30]) must be set to
enable this event. The event causes an ERR if BMM (bit 2) is cleared.
17
TARE
Target Abort Received Event (Read/Write-1-to-Clear). This bit is asserted due to the
reception of a target abort on PCI. Write 1 to clear. TARE (MSR 50002010h[29]) must be
set to enable this event. The event causes an ERR if TARM (bit 1) is cleared.
reception of a target abort on PCI. Write 1 to clear. TARE (MSR 50002010h[29]) must be
set to enable this event. The event causes an ERR if TARM (bit 1) is cleared.
16
MARE
Master Abort Received Event (Read/Write-1-to-Clear). This bit is asserted due to the
reception of a master abort on PCI. Write 1 to clear. MARE (MSR 50002010h[28]) must
be set to enable this event. The event causes an ERR if MARM (bit 0) is cleared.
reception of a master abort on PCI. Write 1 to clear. MARE (MSR 50002010h[28]) must
be set to enable this event. The event causes an ERR if MARM (bit 0) is cleared.
15:6
RSVD (RO)
Reserved (Read Only). Reserved for future use.
5
PARM
Parity Error Mask. Clear to allow PARE (bit 21) to generate an ERR.
4
SYSM
System Error Mask. Clear to allow SYSE (bit 20) to generate an ERR.
3
RSVD (RO)
Reserved (Read Only). Reserved for future use.
2
BMM
Broken Master Mask. Clear to allow BME (bit 18) to generate an ERR.
1
TARM
Target Abort Received Mask. Clear to allow TARE (bit 17) to assert ERR.
0
MARM
Master Abort Received Mask. Clear to allow MARE (bit 16) to assert ERR.