Справочник Пользователя для AMD LX 800@0.9W
AMD Geode™ LX Processors Data Book
59
GLIU Register Descriptions
33234H
4.2.1.5
GLD Power Management MSR (GLD_MSR_PM)
8
EMASK8
Request Comparator Error Mask 1. Write 0 to enable EFLAG8 (bit 40) and to allow a
Request Comparator 1 (RQ_COMPARE_VAL1, GLIU0 MSR 100000C2h, GLIU1 MSR
400000C2h) event to generate an ERR
Request Comparator 1 (RQ_COMPARE_VAL1, GLIU0 MSR 100000C2h, GLIU1 MSR
400000C2h) event to generate an ERR
7
EMASK7
Request Comparator Error Mask 0. Write 0 to enable EFLAG7 (bit 39) and to allow a
Request Comparator 0 (RQ_COMPARE_VAL0, GLIU0 MSR 100000C0h, GLIU1 MSR
400000C0h) event to generate an ERR
Request Comparator 0 (RQ_COMPARE_VAL0, GLIU0 MSR 100000C0h, GLIU1 MSR
400000C0h) event to generate an ERR
6
EMASK6
Statistic Counter Error Mask 3. Write 0 to enable EFLAG6 (bit 38) and to allow a Statis-
tic Counter 3 (GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh) event to generate an
ERR.
tic Counter 3 (GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh) event to generate an
ERR.
5
EMASK5
Statistic Counter Error Mask 2. Write 0 to enable EFLAG5 (bit 37) and to allow a Statis-
tic Counter 2 (GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h) event to generate an
ERR.
tic Counter 2 (GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h) event to generate an
ERR.
4
EMASK4
Statistic Counter Error Mask 1. Write 0 to enable EFLAG4 (bit 36) and to allow a Statis-
tic Counter 1 (GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h) event to generate an
ERR.
tic Counter 1 (GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h) event to generate an
ERR.
3
EMASK3
Statistic Counter Error Mask 0. Write 0 to enable EFLAG3 (bit 35) and to allow a Statis-
tic Counter 0 (GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event to generate an
ERR.
tic Counter 0 (GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event to generate an
ERR.
2
EMASK2
Unhandled SMI Error Mask 2. Write 0 to enable EFLAG2 (bit 34) and to allow the
unhandled SSMI (synchronous error) event to generate an ERR.
unhandled SSMI (synchronous error) event to generate an ERR.
1
EMASK1
Unexpected Address Error Mask 1. as Write 0 to enable EFLAG1 (bit 33) and to allow
the unexpected address (synchronous error) event to generate an ERR.
the unexpected address (synchronous error) event to generate an ERR.
0
EMASK0
Unexpected Type Error Mask 0. Write 0 to enable EFLAG0 (bit 32) and to allow the
unexpected type (synchronous error) event to generate an ERR.
unexpected type (synchronous error) event to generate an ERR.
MSR Address
GLIU0: 10002004h
GLIU1: 40002004h
GLIU1: 40002004h
Type
R/W
Reset Value
00000000_00000000h
GLD
_MSR_ERROR Bit Descriptions (Continued)
Bit
Name
Description
GLD
_MSR_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
PMODE_1
PMODE_0