Справочник Пользователя для AMD LX 800@0.9W
AMD Geode™ LX Processors Data Book
87
GLIU Register Descriptions
33234H
4.2.6.2
IOD Swiss Cheese Descriptors (IOD_SC)
See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
GLIU0
IOD_SC[0:5]
MSR Address
100000E3h-100000E8h
Type
R/W
Reset Value
00000000_00000000h
GLIU1
IOD_SC[0:3]
MSR Address
400000E3h-400000E6h
Type
R/W
Reset Value
00000000_00000000h
IOD_SC[x] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
IDID1
ICMP_BIZ
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
EN
RSVD
WE
N
RE
N
IBASE
RSVD
IOD_SC[x] Bit Descriptions
Bit
Name
Description
63:61
IDID1
Descriptor Destination ID 1. Encoded port number of the destination of addresses
which produce a ‘hit’ based on the other fields in this descriptor.
which produce a ‘hit’ based on the other fields in this descriptor.
60
ICMP_BIZ
Compare Bizzaro Flag. Used to check that the Bizzaro flag of the request is equal to
the PICMP_BIZ_SC bit (this bit). If a match does not occur, then the incoming request
cannot generate a hit. The Bizzaro flag, if set in the incoming request, signifies a “spe-
cial’ cycle such as a PCI Shutdown or Halt.
the PICMP_BIZ_SC bit (this bit). If a match does not occur, then the incoming request
cannot generate a hit. The Bizzaro flag, if set in the incoming request, signifies a “spe-
cial’ cycle such as a PCI Shutdown or Halt.
59:32
RSVD
Reserved. Write as read.
31:24
EN
Enable for Hits to IDID1 or else SUBP. Setting these bits enables hits to IDID1. If not
enabled, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR GLIU0:
10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configuration MSR
(GLD_MSR_CONFIG)" on page 55 for bit descriptions).
enabled, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR GLIU0:
10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configuration MSR
(GLD_MSR_CONFIG)" on page 55 for bit descriptions).
23:22
RSVD
Reserved.
21
WEN
Descriptor Hits IDID1 on Write Request Types else SUBP. If set, causes the incom-
ing request to be routed to the port specified in IDID1 if the incoming request is a Write
type. If not set, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR
GLIU0: 10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configura-
tion MSR (GLD_MSR_CONFIG)" on page 55 for bit descriptions).
ing request to be routed to the port specified in IDID1 if the incoming request is a Write
type. If not set, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR
GLIU0: 10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configura-
tion MSR (GLD_MSR_CONFIG)" on page 55 for bit descriptions).
20
REN
Descriptors Hit IDID1 on Read Request Types else SUBP. If set, causes the incom-
ing request to be routed to the port specified in IDID1 if the incoming request is a Read
type. If not set, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR
GLIU0: 10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configura-
tion MSR (GLD_MSR_CONFIG)" on page 55 for bit descriptions).
ing request to be routed to the port specified in IDID1 if the incoming request is a Read
type. If not set, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR
GLIU0: 10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configura-
tion MSR (GLD_MSR_CONFIG)" on page 55 for bit descriptions).
19:3
IBASE
I/O Memory Base. This field forms the basis of comparison with the incoming checks
that the physical address supplied by the device’s request on address bits [31:18] are
equal to the PBASE field of descriptor register bits [13:0].
that the physical address supplied by the device’s request on address bits [31:18] are
equal to the PBASE field of descriptor register bits [13:0].
2:0
RSVD
Reserved. Write as read.