Справочник Пользователя для AMD LX 800@0.9W
AMD Geode™ LX Processors Data Book
99
CPU Core Register Descriptions
33234H
5.5
CPU Core Register Descriptions
All CPU Core registers are Model Specific Registers
(MSRs) and are accessed via the RDMSR and WRMSR
instructions.
(MSRs) and are accessed via the RDMSR and WRMSR
instructions.
Each module inside the processor is assigned a 256 regis-
ter section of the address space. The module responds to
any reads or writes in that range. Unused addresses within
a module’s address space are reserved, meaning the mod-
ule returns zeroes on a read and ignores writes. Addresses
that are outside all the module address spaces are invalid,
ter section of the address space. The module responds to
any reads or writes in that range. Unused addresses within
a module’s address space are reserved, meaning the mod-
ule returns zeroes on a read and ignores writes. Addresses
that are outside all the module address spaces are invalid,
meaning a RDMSR/WRMSR instruction attempting to use
the address generates a General Protection Fault.
the address generates a General Protection Fault.
The registers associated with the CPU Core are the Stan-
dard GeodeLink™ Device MSRs and CPU Core Specific
MSRs. Table 5-12 and Table 5-13 are register summary
tables that include reset values and page references where
the bit descriptions are provided. Note that the standard
GLD MSRs for the CPU Core start at 00002000h.
dard GeodeLink™ Device MSRs and CPU Core Specific
MSRs. Table 5-12 and Table 5-13 are register summary
tables that include reset values and page references where
the bit descriptions are provided. Note that the standard
GLD MSRs for the CPU Core start at 00002000h.
Table 5-12. Standard GeodeLink™ Device MSRs Summary
MSR
Address
Type
Register Name
Reset Value
Reference
GLD SMI MSR (GLD_MSR_SMI) - Not Used
GLD Error MSR (GLD_MSR_ERROR) - Not Used
Table 5-13. CPU Core Specific MSRs Summary
MSR
Address
Type
Register Name
Reset Value
Reference